10a5a44b81
DQCE and DCS primitives are added.
DQCE allows the internal logic to enable or disable the clock network in
the quadrant. When clock network is disabled, all logic drivern by this
clock is no longer toggled, thus reducing the total power consumtion of
the device.
DCS allows you to select one of four sources for two clock wires (6 and 7).
Wires 6 and 7 have not been used up to this point.
Since "hardware" primitives operate strictly in their own quadrants,
user-specified primitives are converted into one or more "hardware"
primitives as needed.
Also:
- minor edits to make the most of helper functions like connectPorts()
- when creating bases, the corresponding constants are assigned to the
VCC and GND wires, but for now huge nodes are used because, for an
unknown reason, the constants mechanism makes large examples
inoperable. So for now we remain on the nodes.
Compatible with older Apicula databases.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
200 lines
5.6 KiB
C++
200 lines
5.6 KiB
C++
#ifndef GOWIN_H
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#define GOWIN_H
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#include "nextpnr.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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// Return true if a cell is a LUT
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inline bool type_is_lut(IdString cell_type) { return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4); }
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inline bool is_lut(const CellInfo *cell) { return type_is_lut(cell->type); }
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// Return true if a cell is a DFF
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inline bool type_is_dff(IdString cell_type)
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{
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return cell_type.in(id_DFF, id_DFFE, id_DFFN, id_DFFNE, id_DFFS, id_DFFSE, id_DFFNS, id_DFFNSE, id_DFFR, id_DFFRE,
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id_DFFNR, id_DFFNRE, id_DFFP, id_DFFPE, id_DFFNP, id_DFFNPE, id_DFFC, id_DFFCE, id_DFFNC,
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id_DFFNCE);
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}
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inline bool is_dff(const CellInfo *cell) { return type_is_dff(cell->type); }
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// Return true if a cell is a ALU
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inline bool type_is_alu(IdString cell_type) { return cell_type == id_ALU; }
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inline bool is_alu(const CellInfo *cell) { return type_is_alu(cell->type); }
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inline bool type_is_diffio(IdString cell_type)
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{
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return cell_type.in(id_ELVDS_IOBUF, id_ELVDS_IBUF, id_ELVDS_TBUF, id_ELVDS_OBUF, id_TLVDS_IOBUF, id_TLVDS_IBUF,
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id_TLVDS_TBUF, id_TLVDS_OBUF);
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}
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inline bool is_diffio(const CellInfo *cell) { return type_is_diffio(cell->type); }
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// IOLOGIC input and output separately
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inline bool type_is_iologico(IdString cell_type)
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{
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return cell_type.in(id_ODDR, id_ODDRC, id_OSER4, id_OSER8, id_OSER10, id_OVIDEO);
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}
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inline bool is_iologico(const CellInfo *cell) { return type_is_iologico(cell->type); }
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inline bool type_is_iologici(IdString cell_type)
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{
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return cell_type.in(id_IDDR, id_IDDRC, id_IDES4, id_IDES8, id_IDES10, id_IVIDEO);
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}
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inline bool is_iologici(const CellInfo *cell) { return type_is_iologici(cell->type); }
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// Return true if a cell is a SSRAM
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inline bool type_is_ssram(IdString cell_type) { return cell_type.in(id_RAM16SDP1, id_RAM16SDP2, id_RAM16SDP4); }
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inline bool is_ssram(const CellInfo *cell) { return type_is_ssram(cell->type); }
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// Return true if a cell is a BSRAM
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inline bool type_is_bsram(IdString cell_type)
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{
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return cell_type.in(id_SP, id_SPX9, id_pROM, id_pROMX9, id_ROM, id_SDP, id_SDPB, id_SDPX9B, id_DP, id_DPB,
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id_DPX9B);
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}
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inline bool is_bsram(const CellInfo *cell) { return type_is_bsram(cell->type); }
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// Return true if a cell is a DSP
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inline bool type_is_dsp(IdString cell_type)
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{
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return cell_type.in(id_PADD9, id_PADD18, id_MULT9X9, id_MULT18X18, id_MULT36X36, id_ALU54D, id_MULTALU18X18,
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id_MULTALU36X18, id_MULTADDALU18X18);
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}
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inline bool is_dsp(const CellInfo *cell) { return type_is_dsp(cell->type); }
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// ==========================================
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// extra data in the chip db
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// ==========================================
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NPNR_PACKED_STRUCT(struct Pad_extra_data_POD {
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int32_t pll_tile;
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int32_t pll_bel;
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int32_t pll_type;
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});
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NPNR_PACKED_STRUCT(struct Tile_extra_data_POD {
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int32_t class_id;
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int16_t io16_x_off;
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int16_t io16_y_off;
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});
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NPNR_PACKED_STRUCT(struct Bottom_io_cnd_POD {
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int32_t wire_a_net;
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int32_t wire_b_net;
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});
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NPNR_PACKED_STRUCT(struct Bottom_io_POD {
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// simple OBUF
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static constexpr int8_t NORMAL = 0;
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// DDR
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static constexpr int8_t DDR = 1;
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RelSlice<Bottom_io_cnd_POD> conditions;
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});
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NPNR_PACKED_STRUCT(struct Spine_bel_POD {
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int32_t spine;
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int32_t bel_x;
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int32_t bel_y;
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int32_t bel_z;
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});
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NPNR_PACKED_STRUCT(struct Extra_chip_data_POD {
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int32_t chip_flags;
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Bottom_io_POD bottom_io;
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RelSlice<IdString> diff_io_types;
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RelSlice<Spine_bel_POD> dqce_bels;
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RelSlice<Spine_bel_POD> dcs_bels;
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// chip flags
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static constexpr int32_t HAS_SP32 = 1;
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static constexpr int32_t NEED_SP_FIX = 2;
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static constexpr int32_t NEED_BSRAM_OUTREG_FIX = 4;
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static constexpr int32_t NEED_BLKSEL_FIX = 8;
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static constexpr int32_t HAS_BANDGAP = 16;
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});
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} // namespace
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// Bels Z ranges. It is desirable that these numbers be synchronized with the chipdb generator
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namespace BelZ {
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enum
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{
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LUT0_Z = 0,
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LUT7_Z = 14,
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MUX20_Z = 16,
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MUX21_Z = 18,
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MUX23_Z = 22,
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MUX27_Z = 29,
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ALU0_Z = 30, // :35, 6 ALU
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RAMW_Z = 36, // RAM16SDP4
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IOBA_Z = 50,
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IOBB_Z = 51, // +IOBC...IOBL
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IOLOGICA_Z = 70,
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IDES16_Z = 74,
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OSER16_Z = 75,
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BUFG_Z = 76, // : 81 reserve just in case
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BSRAM_Z = 100,
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OSC_Z = 274,
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PLL_Z = 275,
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GSR_Z = 276,
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VCC_Z = 277,
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VSS_Z = 278,
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BANDGAP_Z = 279,
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DQCE_Z = 280, // : 286 reserve for 6 DQCEs
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DCS_Z = 286, // : 287 reserve for 2 DCSs
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// The two least significant bits encode Z for 9-bit adders and
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// multipliers, if they are equal to 0, then we get Z of their common
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// 18-bit equivalent.
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DSP_Z = 509, // DSP
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DSP_0_Z = 511, // DSP macro 0
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PADD18_0_0_Z = 512,
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PADD9_0_0_Z = 512 + 1,
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PADD9_0_1_Z = 512 + 2,
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PADD18_0_1_Z = 516,
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PADD9_0_2_Z = 516 + 1,
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PADD9_0_3_Z = 516 + 2,
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MULT18X18_0_0_Z = 520,
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MULT9X9_0_0_Z = 520 + 1,
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MULT9X9_0_1_Z = 520 + 2,
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MULT18X18_0_1_Z = 524,
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MULT9X9_0_2_Z = 524 + 1,
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MULT9X9_0_3_Z = 524 + 2,
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ALU54D_0_Z = 524 + 3,
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MULTALU18X18_0_Z = 528,
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MULTALU36X18_0_Z = 528 + 1,
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MULTADDALU18X18_0_Z = 528 + 2,
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MULT36X36_Z = 528 + 3,
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DSP_1_Z = 543, // DSP macro 1
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PADD18_1_0_Z = 544,
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PADD9_1_0_Z = 544 + 1,
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PADD9_1_1_Z = 544 + 2,
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PADD18_1_1_Z = 548,
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PADD9_1_2_Z = 548 + 1,
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PADD9_1_3_Z = 548 + 2,
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MULT18X18_1_0_Z = 552,
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MULT9X9_1_0_Z = 552 + 1,
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MULT9X9_1_1_Z = 552 + 2,
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MULT18X18_1_1_Z = 556,
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MULT9X9_1_2_Z = 556 + 1,
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MULT9X9_1_3_Z = 556 + 2,
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ALU54D_1_Z = 556 + 3,
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MULTALU18X18_1_Z = 560,
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MULTALU36X18_1_Z = 560 + 1,
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MULTADDALU18X18_1_Z = 560 + 2
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};
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}
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NEXTPNR_NAMESPACE_END
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#endif
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