YRabbit 11d335c7ce Gowin. Fix GW2A-18(c) DCS and DQCE ... We filter out PIPs from these chips that bypass DCS. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>		2024-08-02 14:12:16 +02:00
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CMakeLists.txt	gowin: Himbaechel. Add GW1NZ-1 BSRAM.	2023-11-26 13:08:09 +01:00
constids.inc	Gowin. Fix GW2A-18(c) DCS and DQCE	2024-08-02 14:12:16 +02:00
cst.cc	gowin: Himbaechel. Extend clock router	2023-09-08 09:15:35 +02:00
cst.h	gowin: Himbaechel. Add constraint file processing.	2023-08-31 08:28:09 +02:00
globals.cc	Gowin. Fix GW2A-18(c) DCS and DQCE	2024-08-02 14:12:16 +02:00
globals.h	gowin: Himbaechel. Add a clock router.	2023-08-31 08:28:09 +02:00
gowin_arch_gen.py	Gowin. Implement clock management primitives.	2024-08-02 14:12:16 +02:00
gowin_utils.cc	Gowin. Implement clock management primitives.	2024-08-02 14:12:16 +02:00
gowin_utils.h	Gowin. Implement clock management primitives.	2024-08-02 14:12:16 +02:00
gowin.cc	Gowin. Implement clock management primitives.	2024-08-02 14:12:16 +02:00
gowin.h	Gowin. Implement clock management primitives.	2024-08-02 14:12:16 +02:00
pack.cc	Gowin. Implement clock management primitives.	2024-08-02 14:12:16 +02:00
pack.h	gowin: Himbaechel. Add ALU.	2023-08-31 08:28:09 +02:00