12 lines
278 B
Verilog
12 lines
278 B
Verilog
module top(input a_pin, output [3:0] led_pin);
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wire a;
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wire [3:0] led;
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TRELLIS_IO #(.DIR("INPUT")) a_buf (.B(a_pin), .O(a));
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf [3:0] (.B(led_pin), .I(led));
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//assign led[0] = !a;
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always @(posedge a) led[0] <= !led[0];
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endmodule
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