395 lines
14 KiB
Python
395 lines
14 KiB
Python
#!/usr/bin/env python3
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import argparse
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import json
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import sys
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from os import path
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tiletype_names = dict()
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parser = argparse.ArgumentParser(description="import MachXO2 routing and bels from Project Trellis")
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parser.add_argument("device", type=str, help="target device")
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parser.add_argument("-p", "--constids", type=str, help="path to constids.inc")
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parser.add_argument("-g", "--gfxh", type=str, help="path to gfx.h (unused)")
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parser.add_argument("-L", "--libdir", type=str, action="append", help="extra Python library path")
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args = parser.parse_args()
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sys.path += args.libdir
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import pytrellis
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import database
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# Get the index for a tiletype
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def get_tiletype_index(name):
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if name in tiletype_names:
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return tiletype_names[name]
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idx = len(tiletype_names)
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tiletype_names[name] = idx
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return idx
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constids = dict()
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class BinaryBlobAssembler:
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def l(self, name, ltype = None, export = False):
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if ltype is None:
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print("label %s" % (name,))
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else:
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print("label %s %s" % (name, ltype))
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def r(self, name, comment):
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if comment is None:
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print("ref %s" % (name,))
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else:
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print("ref %s %s" % (name, comment))
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def s(self, s, comment):
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assert "|" not in s
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print("str |%s| %s" % (s, comment))
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def u8(self, v, comment):
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if comment is None:
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print("u8 %d" % (v,))
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else:
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print("u8 %d %s" % (v, comment))
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def u16(self, v, comment):
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if comment is None:
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print("u16 %d" % (v,))
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else:
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print("u16 %d %s" % (v, comment))
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def u32(self, v, comment):
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if comment is None:
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print("u32 %d" % (v,))
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else:
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print("u32 %d %s" % (v, comment))
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def pre(self, s):
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print("pre %s" % s)
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def post(self, s):
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print("post %s" % s)
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def push(self, name):
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print("push %s" % name)
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def pop(self):
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print("pop")
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def get_bel_index(rg, loc, name):
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tile = rg.tiles[loc]
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idx = 0
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for bel in tile.bels:
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if rg.to_str(bel.name) == name:
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return idx
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idx += 1
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# FIXME: I/O pins can be missing in various rows. Is there a nice way to
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# assert on each device size?
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return None
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packages = {}
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pindata = []
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def process_pio_db(rg, device):
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piofile = path.join(database.get_db_root(), dev_family[device], dev_names[device], "iodb.json")
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with open(piofile, 'r') as f:
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piodb = json.load(f)
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for pkgname, pkgdata in sorted(piodb["packages"].items()):
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pins = []
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for name, pinloc in sorted(pkgdata.items()):
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x = pinloc["col"]
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y = pinloc["row"]
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if x == 0 or x == max_col:
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# FIXME: Oversight in read_pinout.py. We use 0-based
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# columns for 0 and max row, but we otherwise extract
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# the names from the CSV, and...
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loc = pytrellis.Location(x, y)
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else:
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# Lattice uses 1-based columns!
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loc = pytrellis.Location(x - 1, y)
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pio = "PIO" + pinloc["pio"]
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bel_idx = get_bel_index(rg, loc, pio)
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if bel_idx is not None:
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pins.append((name, loc, bel_idx))
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packages[pkgname] = pins
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for metaitem in piodb["pio_metadata"]:
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x = metaitem["col"]
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y = metaitem["row"]
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if x == 0 or x == max_col:
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loc = pytrellis.Location(x, y)
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else:
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loc = pytrellis.Location(x - 1, y)
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pio = "PIO" + metaitem["pio"]
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bank = metaitem["bank"]
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if "function" in metaitem:
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pinfunc = metaitem["function"]
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else:
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pinfunc = None
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dqs = -1
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if "dqs" in metaitem:
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pass
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# tdqs = metaitem["dqs"]
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# if tdqs[0] == "L":
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# dqs = 0
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# elif tdqs[0] == "R":
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# dqs = 2048
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# suffix_size = 0
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# while tdqs[-(suffix_size+1)].isdigit():
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# suffix_size += 1
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# dqs |= int(tdqs[-suffix_size:])
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bel_idx = get_bel_index(rg, loc, pio)
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if bel_idx is not None:
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pindata.append((loc, bel_idx, bank, pinfunc, dqs))
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def write_database(dev_name, chip, rg, endianness):
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def write_loc(loc, sym_name):
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bba.u16(loc.x, "%s.x" % sym_name)
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bba.u16(loc.y, "%s.y" % sym_name)
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# Use Lattice naming conventions, so convert to 1-based col indexing.
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def get_wire_name(loc, idx):
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tile = rg.tiles[loc]
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return "R{}C{}_{}".format(loc.y, loc.x + 1, rg.to_str(tile.wires[idx].name))
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# Before doing anything, ensure sorted routing graph iteration matches
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# y, x
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loc_iter = list(sorted(rg.tiles, key=lambda l : (l.y, l.x)))
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i = 1 # Drop (-2, -2) location.
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for y in range(0, max_row+1):
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for x in range(0, max_col+1):
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l = loc_iter[i]
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assert((y, x) == (l.y, l.x))
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i = i + 1
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bba = BinaryBlobAssembler()
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bba.pre('#include "nextpnr.h"')
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bba.pre('#include "embed.h"')
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bba.pre('NEXTPNR_NAMESPACE_BEGIN')
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bba.post('EmbeddedFile chipdb_file_%s("machxo2/chipdb-%s.bin", chipdb_blob_%s);' % (dev_name, dev_name, dev_name))
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bba.post('NEXTPNR_NAMESPACE_END')
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bba.push("chipdb_blob_%s" % args.device)
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bba.r("chip_info", "chip_info")
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# Nominally should be in order, but support situations where python
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# decides to iterate over rg.tiles out-of-order.
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for l in loc_iter:
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t = rg.tiles[l]
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# Do not include special globals location for now.
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if (l.x, l.y) == (-2, -2):
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continue
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if len(t.arcs) > 0:
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bba.l("loc%d_%d_pips" % (l.y, l.x), "PipInfoPOD")
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for arc in t.arcs:
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write_loc(arc.srcWire.rel, "src")
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write_loc(arc.sinkWire.rel, "dst")
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bba.u32(arc.srcWire.id, "src_idx {}".format(get_wire_name(arc.srcWire.rel, arc.srcWire.id)))
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bba.u32(arc.sinkWire.id, "dst_idx {}".format(get_wire_name(arc.sinkWire.rel, arc.sinkWire.id)))
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src_name = get_wire_name(arc.srcWire.rel, arc.srcWire.id)
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snk_name = get_wire_name(arc.sinkWire.rel, arc.sinkWire.id)
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# TODO: ECP5 timing-model-specific. Reuse for MachXO2?
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# bba.u32(get_pip_class(src_name, snk_name), "timing_class")
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bba.u32(0, "timing_class")
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bba.u16(get_tiletype_index(rg.to_str(arc.tiletype)), "tile_type")
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cls = arc.cls
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bba.u8(arc.cls, "pip_type")
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bba.u8(0, "padding")
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if len(t.wires) > 0:
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for wire_idx in range(len(t.wires)):
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wire = t.wires[wire_idx]
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if len(wire.arcsDownhill) > 0:
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bba.l("loc%d_%d_wire%d_downpips" % (l.y, l.x, wire_idx), "PipLocatorPOD")
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for dp in wire.arcsDownhill:
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write_loc(dp.rel, "rel_loc")
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bba.u32(dp.id, "index")
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if len(wire.arcsUphill) > 0:
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bba.l("loc%d_%d_wire%d_uppips" % (l.y, l.x, wire_idx), "PipLocatorPOD")
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for up in wire.arcsUphill:
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write_loc(up.rel, "rel_loc")
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bba.u32(up.id, "index")
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if len(wire.belPins) > 0:
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bba.l("loc%d_%d_wire%d_belpins" % (l.y, l.x, wire_idx), "BelPortPOD")
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for bp in wire.belPins:
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write_loc(bp.bel.rel, "rel_bel_loc")
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bba.u32(bp.bel.id, "bel_index")
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bba.u32(constids[rg.to_str(bp.pin)], "port")
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bba.l("loc%d_%d_wires" % (l.y, l.x), "WireInfoPOD")
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for wire_idx in range(len(t.wires)):
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wire = t.wires[wire_idx]
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bba.s(rg.to_str(wire.name), "name")
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# TODO: Padding until GUI support is added.
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# bba.u32(constids[wire_type(ddrg.to_str(wire.name))], "type")
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# if ("TILE_WIRE_" + ddrg.to_str(wire.name)) in gfx_wire_ids:
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# bba.u32(gfx_wire_ids["TILE_WIRE_" + ddrg.to_str(wire.name)], "tile_wire")
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# else:
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bba.u32(0, "tile_wire")
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bba.u32(len(wire.arcsUphill), "num_uphill")
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bba.u32(len(wire.arcsDownhill), "num_downhill")
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bba.r("loc%d_%d_wire%d_uppips" % (l.y, l.x, wire_idx) if len(wire.arcsUphill) > 0 else None, "pips_uphill")
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bba.r("loc%d_%d_wire%d_downpips" % (l.y, l.x, wire_idx) if len(wire.arcsDownhill) > 0 else None, "pips_downhill")
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bba.u32(len(wire.belPins), "num_bel_pins")
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bba.r("loc%d_%d_wire%d_belpins" % (l.y, l.x, wire_idx) if len(wire.belPins) > 0 else None, "bel_pins")
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if len(t.bels) > 0:
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for bel_idx in range(len(t.bels)):
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bel = t.bels[bel_idx]
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bba.l("loc%d_%d_bel%d_wires" % (l.y, l.x, bel_idx), "BelWirePOD")
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for pin in bel.wires:
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write_loc(pin.wire.rel, "rel_wire_loc")
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bba.u32(pin.wire.id, "wire_index")
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bba.u32(constids[rg.to_str(pin.pin)], "port")
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bba.u32(int(pin.dir), "dir")
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bba.l("loc%d_%d_bels" % (l.y, l.x), "BelInfoPOD")
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for bel_idx in range(len(t.bels)):
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bel = t.bels[bel_idx]
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bba.s(rg.to_str(bel.name), "name")
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bba.u32(constids[rg.to_str(bel.type)], "type")
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bba.u32(bel.z, "z")
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bba.u32(len(bel.wires), "num_bel_wires")
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bba.r("loc%d_%d_bel%d_wires" % (l.y, l.x, bel_idx), "bel_wires")
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bba.l("tiles", "TileTypePOD")
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for l in loc_iter:
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t = rg.tiles[l]
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if (l.y, l.x) == (-2, -2):
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continue
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bba.u32(len(t.bels), "num_bels")
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bba.u32(len(t.wires), "num_wires")
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bba.u32(len(t.arcs), "num_pips")
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bba.r("loc%d_%d_bels" % (l.y, l.x) if len(t.bels) > 0 else None, "bel_data")
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bba.r("loc%d_%d_wires" % (l.y, l.x) if len(t.wires) > 0 else None, "wire_data")
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bba.r("loc%d_%d_pips" % (l.y, l.x) if len(t.arcs) > 0 else None, "pips_data")
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for y in range(0, max_row+1):
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for x in range(0, max_col+1):
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bba.l("tile_info_%d_%d" % (x, y), "TileNamePOD")
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for tile in chip.get_tiles_by_position(y, x):
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bba.s(tile.info.name, "name")
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bba.u16(get_tiletype_index(tile.info.type), "type_idx")
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bba.u16(0, "padding")
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bba.l("tiles_info", "TileInfoPOD")
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for y in range(0, max_row+1):
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for x in range(0, max_col+1):
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bba.u32(len(chip.get_tiles_by_position(y, x)), "num_tiles")
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bba.r("tile_info_%d_%d" % (x, y), "tile_names")
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for package, pkgdata in sorted(packages.items()):
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bba.l("package_data_%s" % package, "PackagePinPOD")
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for pin in pkgdata:
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name, loc, bel_idx = pin
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bba.s(name, "name")
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write_loc(loc, "abs_loc")
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bba.u32(bel_idx, "bel_index")
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bba.l("package_data", "PackageInfoPOD")
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for package, pkgdata in sorted(packages.items()):
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bba.s(package, "name")
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bba.u32(len(pkgdata), "num_pins")
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bba.r("package_data_%s" % package, "pin_data")
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bba.l("pio_info", "PIOInfoPOD")
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for pin in pindata:
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loc, bel_idx, bank, func, dqs = pin
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write_loc(loc, "abs_loc")
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bba.u32(bel_idx, "bel_index")
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if func is not None and func != "WRITEN":
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bba.s(func, "function_name")
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else:
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bba.r(None, "function_name")
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# TODO: io_grouping? And DQS.
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bba.u16(bank, "bank")
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bba.u16(dqs, "dqsgroup")
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bba.l("tiletype_names", "RelPtr<char>")
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for tt, idx in sorted(tiletype_names.items(), key=lambda x: x[1]):
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bba.s(tt, "name")
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bba.l("chip_info")
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bba.u32(max_col + 1, "width")
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bba.u32(max_row + 1, "height")
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bba.u32((max_col + 1) * (max_row + 1), "num_tiles")
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bba.u32(len(packages), "num_packages")
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bba.u32(len(pindata), "num_pios")
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bba.u32(const_id_count, "const_id_count")
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bba.r("tiles", "tiles")
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bba.r("tiletype_names", "tiletype_names")
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bba.r("package_data", "package_info")
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bba.r("pio_info", "pio_info")
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bba.r("tiles_info", "tile_info")
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bba.pop()
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dev_family = {
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"256X": "MachXO",
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"640X": "MachXO",
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"1200X":"MachXO",
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"2280X":"MachXO",
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"256": "MachXO2",
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"640": "MachXO2",
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"1200": "MachXO2",
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"2000": "MachXO2",
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"4000": "MachXO2",
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"7000": "MachXO2"
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}
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dev_names = {
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"256X": "LCMXO256",
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"640X": "LCMXO640",
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"1200X":"LCMXO1200",
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"2280X":"LCMXO2280",
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"256": "LCMXO2-256",
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"640": "LCMXO2-640",
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"1200": "LCMXO2-1200",
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"2000": "LCMXO2-2000",
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"4000": "LCMXO2-4000",
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"7000": "LCMXO2-7000"
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}
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def main():
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global max_row, max_col, const_id_count
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pytrellis.load_database(database.get_db_root())
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args = parser.parse_args()
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const_id_count = 1 # count ID_NONE
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with open(args.constids) as f:
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for line in f:
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line = line.replace("(", " ")
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line = line.replace(")", " ")
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line = line.split()
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if len(line) == 0:
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continue
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assert len(line) == 2
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assert line[0] == "X"
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idx = len(constids) + 1
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constids[line[1]] = idx
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const_id_count += 1
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constids["SLICE"] = constids["FACADE_SLICE"]
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constids["PIO"] = constids["FACADE_IO"]
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chip = pytrellis.Chip(dev_names[args.device])
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rg = pytrellis.make_optimized_chipdb(chip)
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max_row = chip.get_max_row()
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max_col = chip.get_max_col()
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process_pio_db(rg, args.device)
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bba = write_database(args.device, chip, rg, "le")
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if __name__ == "__main__":
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main()
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