198 lines
7.1 KiB
C++
198 lines
7.1 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2023 Myrtle Shah <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "nextpnr.h"
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#include "pack.h"
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#include "pins.h"
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#define HIMBAECHEL_CONSTIDS "uarch/xilinx/constids.inc"
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#include "himbaechel_constids.h"
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NEXTPNR_NAMESPACE_BEGIN
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CellInfo *XilinxPacker::create_cell(IdString type, IdString name)
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{
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CellInfo *cell = ctx->createCell(name, type);
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auto add_port = [&](const std::string &name, PortType dir) {
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IdString id = ctx->id(name);
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cell->ports[id].name = id;
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cell->ports[id].type = dir;
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};
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if (type == id_SLICE_LUTX) {
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for (int i = 1; i <= 6; i++)
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add_port("A" + std::to_string(i), PORT_IN);
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for (int i = 1; i <= 9; i++)
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add_port("WA" + std::to_string(i), PORT_IN);
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add_port("DI1", PORT_IN);
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add_port("DI2", PORT_IN);
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add_port("CLK", PORT_IN);
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add_port("WE", PORT_IN);
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add_port("SIN", PORT_IN);
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add_port("O5", PORT_OUT);
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add_port("O6", PORT_OUT);
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add_port("MC31", PORT_OUT);
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} else if (type == id_SLICE_FFX) {
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add_port("D", PORT_IN);
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add_port("SR", PORT_IN);
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add_port("CE", PORT_IN);
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add_port("CLK", PORT_IN);
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add_port("Q", PORT_OUT);
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} else if (type == id_RAMD64E) {
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for (int i = 0; i < 6; i++)
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add_port("RADR" + std::to_string(i), PORT_IN);
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for (int i = 0; i < 8; i++)
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add_port("WADR" + std::to_string(i), PORT_IN);
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add_port("CLK", PORT_IN);
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add_port("I", PORT_IN);
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add_port("WE", PORT_IN);
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add_port("O", PORT_OUT);
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} else if (type == id_RAMD32) {
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for (int i = 0; i < 5; i++)
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add_port("RADR" + std::to_string(i), PORT_IN);
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for (int i = 0; i < 5; i++)
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add_port("WADR" + std::to_string(i), PORT_IN);
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add_port("CLK", PORT_IN);
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add_port("I", PORT_IN);
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add_port("WE", PORT_IN);
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add_port("O", PORT_OUT);
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} else if (type.in(id_MUXF7, id_MUXF8, id_MUXF9)) {
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add_port("I0", PORT_IN);
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add_port("I1", PORT_IN);
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add_port("S", PORT_IN);
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add_port("O", PORT_OUT);
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} else if (type == id_CARRY8) {
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add_port("CI", PORT_IN);
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add_port("CI_TOP", PORT_IN);
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for (int i = 0; i < 8; i++) {
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add_port("DI[" + std::to_string(i) + "]", PORT_IN);
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add_port("S[" + std::to_string(i) + "]", PORT_IN);
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add_port("CO[" + std::to_string(i) + "]", PORT_OUT);
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add_port("O[" + std::to_string(i) + "]", PORT_OUT);
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}
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} else if (type == id_MUXCY) {
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add_port("CI", PORT_IN);
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add_port("DI", PORT_IN);
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add_port("S", PORT_IN);
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add_port("O", PORT_OUT);
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} else if (type == id_XORCY) {
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add_port("CI", PORT_IN);
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add_port("LI", PORT_IN);
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add_port("O", PORT_OUT);
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} else if (type == id_PAD) {
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add_port("PAD", PORT_INOUT);
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} else if (type == id_INBUF) {
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add_port("VREF", PORT_IN);
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add_port("PAD", PORT_IN);
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add_port("OSC_EN", PORT_IN);
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for (int i = 0; i < 4; i++)
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add_port("OSC[" + std::to_string(i) + "]", PORT_IN);
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add_port("O", PORT_OUT);
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} else if (type == id_IBUFCTRL) {
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add_port("I", PORT_IN);
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add_port("IBUFDISABLE", PORT_IN);
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add_port("T", PORT_IN);
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add_port("O", PORT_OUT);
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} else if (type.in(id_OBUF, id_IBUF)) {
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add_port("I", PORT_IN);
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add_port("O", PORT_OUT);
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} else if (type == id_OBUFT) {
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add_port("I", PORT_IN);
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add_port("T", PORT_IN);
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add_port("O", PORT_OUT);
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} else if (type == id_IOBUF) {
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add_port("I", PORT_IN);
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add_port("T", PORT_IN);
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add_port("O", PORT_OUT);
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add_port("IO", PORT_INOUT);
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} else if (type == id_OBUFT_DCIEN) {
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add_port("I", PORT_IN);
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add_port("T", PORT_IN);
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add_port("DCITERMDISABLE", PORT_IN);
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add_port("O", PORT_OUT);
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} else if (type == id_DIFFINBUF) {
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add_port("DIFF_IN_P", PORT_IN);
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add_port("DIFF_IN_N", PORT_IN);
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add_port("OSC_EN[0]", PORT_IN);
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add_port("OSC_EN[1]", PORT_IN);
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for (int i = 0; i < 4; i++)
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add_port("OSC[" + std::to_string(i) + "]", PORT_IN);
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add_port("VREF", PORT_IN);
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add_port("O", PORT_OUT);
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add_port("O_B", PORT_OUT);
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} else if (type == id_HPIO_VREF) {
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for (int i = 0; i < 7; i++)
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add_port("FABRIC_VREF_TUNE[" + std::to_string(i) + "]", PORT_IN);
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add_port("VREF", PORT_OUT);
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} else if (type == id_INV) {
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add_port("I", PORT_IN);
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add_port("O", PORT_OUT);
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} else if (type == id_IDELAYCTRL) {
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add_port("REFCLK", PORT_IN);
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add_port("RST", PORT_IN);
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add_port("RDY", PORT_OUT);
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} else if (type == id_IBUF) {
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add_port("I", PORT_IN);
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add_port("O", PORT_OUT);
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} else if (type == id_IBUF_INTERMDISABLE) {
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add_port("I", PORT_IN);
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add_port("IBUFDISABLE", PORT_IN);
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add_port("INTERMDISABLE", PORT_IN);
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add_port("O", PORT_OUT);
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} else if (type == id_IBUFDS) {
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add_port("I", PORT_IN);
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add_port("IB", PORT_IN);
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add_port("O", PORT_OUT);
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} else if (type == id_IBUFDS_INTERMDISABLE_INT) {
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add_port("I", PORT_IN);
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add_port("IB", PORT_IN);
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add_port("IBUFDISABLE", PORT_IN);
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add_port("INTERMDISABLE", PORT_IN);
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add_port("O", PORT_OUT);
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} else if (type == id_CARRY4) {
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add_port("CI", PORT_IN);
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add_port("CYINIT", PORT_IN);
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for (int i = 0; i < 4; i++) {
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add_port("DI[" + std::to_string(i) + "]", PORT_IN);
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add_port("S[" + std::to_string(i) + "]", PORT_IN);
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add_port("CO[" + std::to_string(i) + "]", PORT_OUT);
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add_port("O[" + std::to_string(i) + "]", PORT_OUT);
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}
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}
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return cell;
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}
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CellInfo *XilinxPacker::create_lut(const std::string &name, const std::vector<NetInfo *> &inputs, NetInfo *output,
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const Property &init)
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{
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CellInfo *cell = ctx->createCell(ctx->id(name), ctx->idf("LUT%d", int(inputs.size())));
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for (size_t i = 0; i < inputs.size(); i++) {
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IdString ip = ctx->idf("I%d", int(i));
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cell->addInput(ip);
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cell->connectPort(ip, inputs.at(i));
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}
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cell->addOutput(id_O);
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cell->connectPort(id_O, output);
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cell->params[id_INIT] = init;
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return cell;
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}
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NEXTPNR_NAMESPACE_END
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