603 lines
22 KiB
Python
Executable File
603 lines
22 KiB
Python
Executable File
#!/usr/bin/env python3
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import pytrellis
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import database
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import argparse
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import json
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import pip_classes
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import timing_dbs
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from os import path
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location_types = dict()
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type_at_location = dict()
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tiletype_names = dict()
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gfx_wire_ids = dict()
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gfx_wire_names = list()
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parser = argparse.ArgumentParser(description="import ECP5 routing and bels from Project Trellis")
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parser.add_argument("device", type=str, help="target device")
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parser.add_argument("-p", "--constids", type=str, help="path to constids.inc")
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parser.add_argument("-g", "--gfxh", type=str, help="path to gfx.h")
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args = parser.parse_args()
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with open(args.gfxh) as f:
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state = 0
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for line in f:
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if state == 0 and line.startswith("enum GfxTileWireId"):
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state = 1
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elif state == 1 and line.startswith("};"):
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state = 0
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elif state == 1 and (line.startswith("{") or line.strip() == ""):
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pass
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elif state == 1:
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idx = len(gfx_wire_ids)
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name = line.strip().rstrip(",")
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gfx_wire_ids[name] = idx
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gfx_wire_names.append(name)
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def gfx_wire_alias(old, new):
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assert old in gfx_wire_ids
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assert new not in gfx_wire_ids
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gfx_wire_ids[new] = gfx_wire_ids[old]
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def wire_type(name):
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longname = name
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name = name.split('/')
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if name[0].startswith("X") and name[1].startswith("Y"):
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name = name[2:]
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if name[0].endswith("_SLICE"):
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return "WIRE_TYPE_SLICE"
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if name[0].endswith("_DQS"):
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return "WIRE_TYPE_DQS"
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if name[0].endswith("_IOLOGIC"):
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return "WIRE_TYPE_IOLOGIC"
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if name[0].endswith("_SIOLOGIC"):
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return "WIRE_TYPE_SIOLOGIC"
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if name[0].endswith("_PIO"):
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return "WIRE_TYPE_PIO"
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if name[0].endswith("_DDRDLL"):
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return "WIRE_TYPE_DDRDLL"
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if name[0].endswith("_CCLK"):
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return "WIRE_TYPE_CCLK"
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if name[0].endswith("_EXTREF"):
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return "WIRE_TYPE_EXTREF"
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if name[0].endswith("_DCU"):
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return "WIRE_TYPE_DCU"
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if name[0].endswith("_EBR"):
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return "WIRE_TYPE_EBR"
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if name[0].endswith("_MULT18"):
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return "WIRE_TYPE_MULT18"
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if name[0].endswith("_ALU54"):
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return "WIRE_TYPE_ALU54"
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if name[0].startswith("H00"):
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return "WIRE_TYPE_H00"
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if name[0].startswith("H01"):
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return "WIRE_TYPE_H01"
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if name[0].startswith("HFI"):
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return "WIRE_TYPE_H01"
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if name[0].startswith("HL7"):
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return "WIRE_TYPE_H01"
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if name[0].startswith("H02"):
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return "WIRE_TYPE_H02"
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if name[0].startswith("H06"):
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return "WIRE_TYPE_H06"
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if name[0].startswith("V00"):
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return "WIRE_TYPE_V00"
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if name[0].startswith("V01"):
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return "WIRE_TYPE_V01"
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if name[0].startswith("V02"):
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return "WIRE_TYPE_V02"
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if name[0].startswith("V06"):
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return "WIRE_TYPE_V06"
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if name[0].startswith("G_HPBX"):
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return "WIRE_TYPE_G_HPBX"
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return "WIRE_TYPE_NONE"
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def is_global(loc):
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return loc.x == -2 and loc.y == -2
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# Get the index for a tiletype
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def get_tiletype_index(name):
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if name in tiletype_names:
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return tiletype_names[name]
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idx = len(tiletype_names)
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tiletype_names[name] = idx
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return idx
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constids = dict()
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class BinaryBlobAssembler:
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def l(self, name, ltype = None, export = False):
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if ltype is None:
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print("label %s" % (name,))
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else:
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print("label %s %s" % (name, ltype))
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def r(self, name, comment):
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if comment is None:
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print("ref %s" % (name,))
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else:
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print("ref %s %s" % (name, comment))
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def s(self, s, comment):
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assert "|" not in s
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print("str |%s| %s" % (s, comment))
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def u8(self, v, comment):
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if comment is None:
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print("u8 %d" % (v,))
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else:
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print("u8 %d %s" % (v, comment))
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def u16(self, v, comment):
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if comment is None:
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print("u16 %d" % (v,))
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else:
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print("u16 %d %s" % (v, comment))
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def u32(self, v, comment):
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if comment is None:
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print("u32 %d" % (v,))
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else:
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print("u32 %d %s" % (v, comment))
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def pre(self, s):
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print("pre %s" % s)
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def post(self, s):
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print("post %s" % s)
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def push(self, name):
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print("push %s" % name)
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def pop(self):
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print("pop")
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def get_bel_index(ddrg, loc, name):
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loctype = ddrg.locationTypes[ddrg.typeAtLocation[loc]]
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idx = 0
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for bel in loctype.bels:
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if ddrg.to_str(bel.name) == name:
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return idx
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idx += 1
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assert loc.y == max_row # Only missing IO should be special pins at bottom of device
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return None
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packages = {}
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pindata = []
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def process_pio_db(ddrg, device):
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piofile = path.join(database.get_db_root(), "ECP5", dev_names[device], "iodb.json")
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with open(piofile, 'r') as f:
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piodb = json.load(f)
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for pkgname, pkgdata in sorted(piodb["packages"].items()):
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pins = []
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for name, pinloc in sorted(pkgdata.items()):
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x = pinloc["col"]
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y = pinloc["row"]
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loc = pytrellis.Location(x, y)
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pio = "PIO" + pinloc["pio"]
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bel_idx = get_bel_index(ddrg, loc, pio)
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if bel_idx is not None:
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pins.append((name, loc, bel_idx))
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packages[pkgname] = pins
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for metaitem in piodb["pio_metadata"]:
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x = metaitem["col"]
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y = metaitem["row"]
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loc = pytrellis.Location(x, y)
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pio = "PIO" + metaitem["pio"]
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bank = metaitem["bank"]
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if "function" in metaitem:
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pinfunc = metaitem["function"]
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else:
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pinfunc = None
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dqs = -1
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if "dqs" in metaitem:
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tdqs = metaitem["dqs"]
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if tdqs[0] == "L":
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dqs = 0
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elif tdqs[0] == "R":
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dqs = 2048
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suffix_size = 0
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while tdqs[-(suffix_size+1)].isdigit():
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suffix_size += 1
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dqs |= int(tdqs[-suffix_size:])
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bel_idx = get_bel_index(ddrg, loc, pio)
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if bel_idx is not None:
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pindata.append((loc, bel_idx, bank, pinfunc, dqs))
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global_data = {}
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quadrants = ["UL", "UR", "LL", "LR"]
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def process_loc_globals(chip):
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for y in range(0, max_row+1):
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for x in range(0, max_col+1):
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quad = chip.global_data.get_quadrant(y, x)
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tapdrv = chip.global_data.get_tap_driver(y, x)
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if tapdrv.col == x:
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spinedrv = chip.global_data.get_spine_driver(quad, x)
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spine = (spinedrv.second, spinedrv.first)
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else:
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spine = (-1, -1)
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global_data[x, y] = (quadrants.index(quad), int(tapdrv.dir), tapdrv.col, spine)
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speed_grade_names = ["6", "7", "8", "8_5G"]
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speed_grade_cells = {}
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speed_grade_pips = {}
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pip_class_to_idx = {"default": 0, "zero": 1}
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timing_port_xform = {
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"RAD0": "D0",
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"RAD1": "B0",
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"RAD2": "C0",
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"RAD3": "A0",
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}
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def process_timing_data():
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for grade in speed_grade_names:
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with open(timing_dbs.cells_db_path("ECP5", grade)) as f:
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cell_data = json.load(f)
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cells = []
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for cell, cdata in sorted(cell_data.items()):
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celltype = constids[cell.replace(":", "_").replace("=", "_").replace(",", "_")]
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delays = []
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setupholds = []
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for entry in cdata:
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if entry["type"] == "Width":
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continue
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elif entry["type"] == "IOPath":
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from_pin = entry["from_pin"][1] if type(entry["from_pin"]) is list else entry["from_pin"]
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if from_pin in timing_port_xform:
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from_pin = timing_port_xform[from_pin]
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to_pin = entry["to_pin"]
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if to_pin in timing_port_xform:
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to_pin = timing_port_xform[to_pin]
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min_delay = min(entry["rising"][0], entry["falling"][0])
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max_delay = min(entry["rising"][2], entry["falling"][2])
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delays.append((constids[from_pin], constids[to_pin], min_delay, max_delay))
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elif entry["type"] == "SetupHold":
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pin = constids[entry["pin"]]
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clock = constids[entry["clock"][1]]
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min_setup = entry["setup"][0]
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max_setup = entry["setup"][2]
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min_hold = entry["hold"][0]
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max_hold = entry["hold"][2]
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setupholds.append((pin, clock, min_setup, max_setup, min_hold, max_hold))
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else:
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assert False, entry["type"]
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cells.append((celltype, delays, setupholds))
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pip_class_delays = []
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for i in range(len(pip_class_to_idx)):
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pip_class_delays.append((50, 50, 0, 0))
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pip_class_delays[pip_class_to_idx["zero"]] = (0, 0, 0, 0)
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with open(timing_dbs.interconnect_db_path("ECP5", grade)) as f:
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interconn_data = json.load(f)
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for pipclass, pipdata in sorted(interconn_data.items()):
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min_delay = pipdata["delay"][0] * 1.1
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max_delay = pipdata["delay"][2] * 1.1
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min_fanout = pipdata["fanout"][0]
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max_fanout = pipdata["fanout"][2]
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if grade == "6":
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pip_class_to_idx[pipclass] = len(pip_class_delays)
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pip_class_delays.append((min_delay, max_delay, min_fanout, max_fanout))
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else:
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if pipclass in pip_class_to_idx:
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pip_class_delays[pip_class_to_idx[pipclass]] = (min_delay, max_delay, min_fanout, max_fanout)
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speed_grade_cells[grade] = cells
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speed_grade_pips[grade] = pip_class_delays
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def get_pip_class(wire_from, wire_to):
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if "FCO" in wire_from or "FCI" in wire_to:
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return pip_class_to_idx["zero"]
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if "F5" in wire_from or "FX" in wire_from or "FXA" in wire_to or "FXB" in wire_to:
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return pip_class_to_idx["zero"]
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class_name = pip_classes.get_pip_class(wire_from, wire_to)
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if class_name is None or class_name not in pip_class_to_idx:
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class_name = "default"
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return pip_class_to_idx[class_name]
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def write_database(dev_name, chip, ddrg, endianness):
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def write_loc(loc, sym_name):
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bba.u16(loc.x, "%s.x" % sym_name)
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bba.u16(loc.y, "%s.y" % sym_name)
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loctypes = list([_.key() for _ in ddrg.locationTypes])
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loc_with_type = {}
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for y in range(0, max_row+1):
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for x in range(0, max_col+1):
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loc_with_type[loctypes.index(ddrg.typeAtLocation[pytrellis.Location(x, y)])] = (x, y)
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def get_wire_name(arc_loctype, rel, idx):
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loc = loc_with_type[arc_loctype]
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lt = ddrg.typeAtLocation[pytrellis.Location(loc[0] + rel.x, loc[1] + rel.y)]
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wire = ddrg.locationTypes[lt].wires[idx]
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return "R{}C{}_{}".format(loc[1] + rel.y, loc[0] + rel.x, ddrg.to_str(wire.name))
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bba = BinaryBlobAssembler()
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bba.pre('#include "nextpnr.h"')
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bba.pre('NEXTPNR_NAMESPACE_BEGIN')
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bba.post('NEXTPNR_NAMESPACE_END')
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bba.push("chipdb_blob_%s" % dev_name)
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bba.r("chip_info", "chip_info")
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for idx in range(len(loctypes)):
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loctype = ddrg.locationTypes[loctypes[idx]]
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if len(loctype.arcs) > 0:
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bba.l("loc%d_pips" % idx, "PipInfoPOD")
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for arc in loctype.arcs:
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write_loc(arc.srcWire.rel, "src")
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write_loc(arc.sinkWire.rel, "dst")
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bba.u32(arc.srcWire.id, "src_idx")
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bba.u32(arc.sinkWire.id, "dst_idx")
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src_name = get_wire_name(idx, arc.srcWire.rel, arc.srcWire.id)
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snk_name = get_wire_name(idx, arc.sinkWire.rel, arc.sinkWire.id)
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bba.u32(get_pip_class(src_name, snk_name), "timing_class")
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bba.u16(get_tiletype_index(ddrg.to_str(arc.tiletype)), "tile_type")
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cls = arc.cls
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if cls == 1 and "PCS" in snk_name or "DCU" in snk_name or "DCU" in src_name:
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cls = 2
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bba.u8(cls, "pip_type")
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bba.u8(0, "padding")
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if len(loctype.wires) > 0:
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for wire_idx in range(len(loctype.wires)):
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wire = loctype.wires[wire_idx]
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if len(wire.arcsDownhill) > 0:
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bba.l("loc%d_wire%d_downpips" % (idx, wire_idx), "PipLocatorPOD")
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for dp in wire.arcsDownhill:
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write_loc(dp.rel, "rel_loc")
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bba.u32(dp.id, "index")
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if len(wire.arcsUphill) > 0:
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bba.l("loc%d_wire%d_uppips" % (idx, wire_idx), "PipLocatorPOD")
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for up in wire.arcsUphill:
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write_loc(up.rel, "rel_loc")
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bba.u32(up.id, "index")
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if len(wire.belPins) > 0:
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bba.l("loc%d_wire%d_belpins" % (idx, wire_idx), "BelPortPOD")
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for bp in wire.belPins:
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write_loc(bp.bel.rel, "rel_bel_loc")
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bba.u32(bp.bel.id, "bel_index")
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bba.u32(constids[ddrg.to_str(bp.pin)], "port")
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bba.l("loc%d_wires" % idx, "WireInfoPOD")
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for wire_idx in range(len(loctype.wires)):
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wire = loctype.wires[wire_idx]
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bba.s(ddrg.to_str(wire.name), "name")
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bba.u32(constids[wire_type(ddrg.to_str(wire.name))], "type")
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if ("TILE_WIRE_" + ddrg.to_str(wire.name)) in gfx_wire_ids:
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bba.u32(gfx_wire_ids["TILE_WIRE_" + ddrg.to_str(wire.name)], "tile_wire")
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else:
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bba.u32(0, "tile_wire")
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bba.u32(len(wire.arcsUphill), "num_uphill")
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bba.u32(len(wire.arcsDownhill), "num_downhill")
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bba.r("loc%d_wire%d_uppips" % (idx, wire_idx) if len(wire.arcsUphill) > 0 else None, "pips_uphill")
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bba.r("loc%d_wire%d_downpips" % (idx, wire_idx) if len(wire.arcsDownhill) > 0 else None, "pips_downhill")
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bba.u32(len(wire.belPins), "num_bel_pins")
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bba.r("loc%d_wire%d_belpins" % (idx, wire_idx) if len(wire.belPins) > 0 else None, "bel_pins")
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if len(loctype.bels) > 0:
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for bel_idx in range(len(loctype.bels)):
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bel = loctype.bels[bel_idx]
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bba.l("loc%d_bel%d_wires" % (idx, bel_idx), "BelWirePOD")
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for pin in bel.wires:
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write_loc(pin.wire.rel, "rel_wire_loc")
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bba.u32(pin.wire.id, "wire_index")
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bba.u32(constids[ddrg.to_str(pin.pin)], "port")
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bba.u32(int(pin.dir), "dir")
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bba.l("loc%d_bels" % idx, "BelInfoPOD")
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for bel_idx in range(len(loctype.bels)):
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bel = loctype.bels[bel_idx]
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bba.s(ddrg.to_str(bel.name), "name")
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bba.u32(constids[ddrg.to_str(bel.type)], "type")
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bba.u32(bel.z, "z")
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bba.u32(len(bel.wires), "num_bel_wires")
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bba.r("loc%d_bel%d_wires" % (idx, bel_idx), "bel_wires")
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bba.l("locations", "LocationTypePOD")
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for idx in range(len(loctypes)):
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loctype = ddrg.locationTypes[loctypes[idx]]
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bba.u32(len(loctype.bels), "num_bels")
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bba.u32(len(loctype.wires), "num_wires")
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bba.u32(len(loctype.arcs), "num_pips")
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bba.r("loc%d_bels" % idx if len(loctype.bels) > 0 else None, "bel_data")
|
|
bba.r("loc%d_wires" % idx if len(loctype.wires) > 0 else None, "wire_data")
|
|
bba.r("loc%d_pips" % idx if len(loctype.arcs) > 0 else None, "pips_data")
|
|
|
|
for y in range(0, max_row+1):
|
|
for x in range(0, max_col+1):
|
|
bba.l("tile_info_%d_%d" % (x, y), "TileNamePOD")
|
|
for tile in chip.get_tiles_by_position(y, x):
|
|
bba.s(tile.info.name, "name")
|
|
bba.u16(get_tiletype_index(tile.info.type), "type_idx")
|
|
bba.u16(0, "padding")
|
|
|
|
bba.l("tiles_info", "TileInfoPOD")
|
|
for y in range(0, max_row+1):
|
|
for x in range(0, max_col+1):
|
|
bba.u32(len(chip.get_tiles_by_position(y, x)), "num_tiles")
|
|
bba.r("tile_info_%d_%d" % (x, y), "tile_names")
|
|
|
|
bba.l("location_types", "int32_t")
|
|
for y in range(0, max_row+1):
|
|
for x in range(0, max_col+1):
|
|
bba.u32(loctypes.index(ddrg.typeAtLocation[pytrellis.Location(x, y)]), "loctype")
|
|
|
|
bba.l("location_glbinfo", "GlobalInfoPOD")
|
|
for y in range(0, max_row+1):
|
|
for x in range(0, max_col+1):
|
|
bba.u16(global_data[x, y][2], "tap_col")
|
|
bba.u8(global_data[x, y][1], "tap_dir")
|
|
bba.u8(global_data[x, y][0], "quad")
|
|
bba.u16(global_data[x, y][3][1], "spine_row")
|
|
bba.u16(global_data[x, y][3][0], "spine_col")
|
|
|
|
for package, pkgdata in sorted(packages.items()):
|
|
bba.l("package_data_%s" % package, "PackagePinPOD")
|
|
for pin in pkgdata:
|
|
name, loc, bel_idx = pin
|
|
bba.s(name, "name")
|
|
write_loc(loc, "abs_loc")
|
|
bba.u32(bel_idx, "bel_index")
|
|
|
|
bba.l("package_data", "PackageInfoPOD")
|
|
for package, pkgdata in sorted(packages.items()):
|
|
bba.s(package, "name")
|
|
bba.u32(len(pkgdata), "num_pins")
|
|
bba.r("package_data_%s" % package, "pin_data")
|
|
|
|
bba.l("pio_info", "PIOInfoPOD")
|
|
for pin in pindata:
|
|
loc, bel_idx, bank, func, dqs = pin
|
|
write_loc(loc, "abs_loc")
|
|
bba.u32(bel_idx, "bel_index")
|
|
if func is not None:
|
|
bba.s(func, "function_name")
|
|
else:
|
|
bba.r(None, "function_name")
|
|
bba.u16(bank, "bank")
|
|
bba.u16(dqs, "dqsgroup")
|
|
|
|
bba.l("tiletype_names", "RelPtr<char>")
|
|
for tt, idx in sorted(tiletype_names.items(), key=lambda x: x[1]):
|
|
bba.s(tt, "name")
|
|
|
|
for grade in speed_grade_names:
|
|
for cell in speed_grade_cells[grade]:
|
|
celltype, delays, setupholds = cell
|
|
if len(delays) > 0:
|
|
bba.l("cell_%d_delays_%s" % (celltype, grade))
|
|
for delay in delays:
|
|
from_pin, to_pin, min_delay, max_delay = delay
|
|
bba.u32(from_pin, "from_pin")
|
|
bba.u32(to_pin, "to_pin")
|
|
bba.u32(min_delay, "min_delay")
|
|
bba.u32(max_delay, "max_delay")
|
|
if len(setupholds) > 0:
|
|
bba.l("cell_%d_setupholds_%s" % (celltype, grade))
|
|
for sh in setupholds:
|
|
pin, clock, min_setup, max_setup, min_hold, max_hold = sh
|
|
bba.u32(pin, "sig_port")
|
|
bba.u32(clock, "clock_port")
|
|
bba.u32(min_setup, "min_setup")
|
|
bba.u32(max_setup, "max_setup")
|
|
bba.u32(min_hold, "min_hold")
|
|
bba.u32(max_hold, "max_hold")
|
|
bba.l("cell_timing_data_%s" % grade)
|
|
for cell in speed_grade_cells[grade]:
|
|
celltype, delays, setupholds = cell
|
|
bba.u32(celltype, "cell_type")
|
|
bba.u32(len(delays), "num_delays")
|
|
bba.u32(len(setupholds), "num_setup_hold")
|
|
bba.r("cell_%d_delays_%s" % (celltype, grade) if len(delays) > 0 else None, "delays")
|
|
bba.r("cell_%d_setupholds_%s" % (celltype, grade) if len(delays) > 0 else None, "setupholds")
|
|
bba.l("pip_timing_data_%s" % grade)
|
|
for pipclass in speed_grade_pips[grade]:
|
|
min_delay, max_delay, min_fanout, max_fanout = pipclass
|
|
bba.u32(min_delay, "min_delay")
|
|
bba.u32(max_delay, "max_delay")
|
|
bba.u32(min_fanout, "min_fanout")
|
|
bba.u32(max_fanout, "max_fanout")
|
|
bba.l("speed_grade_data")
|
|
for grade in speed_grade_names:
|
|
bba.u32(len(speed_grade_cells[grade]), "num_cell_timings")
|
|
bba.u32(len(speed_grade_pips[grade]), "num_pip_classes")
|
|
bba.r("cell_timing_data_%s" % grade, "cell_timings")
|
|
bba.r("pip_timing_data_%s" % grade, "pip_classes")
|
|
|
|
bba.l("chip_info")
|
|
bba.u32(max_col + 1, "width")
|
|
bba.u32(max_row + 1, "height")
|
|
bba.u32((max_col + 1) * (max_row + 1), "num_tiles")
|
|
bba.u32(len(location_types), "num_location_types")
|
|
bba.u32(len(packages), "num_packages")
|
|
bba.u32(len(pindata), "num_pios")
|
|
|
|
bba.r("locations", "locations")
|
|
bba.r("location_types", "location_type")
|
|
bba.r("location_glbinfo", "location_glbinfo")
|
|
bba.r("tiletype_names", "tiletype_names")
|
|
bba.r("package_data", "package_info")
|
|
bba.r("pio_info", "pio_info")
|
|
bba.r("tiles_info", "tile_info")
|
|
bba.r("speed_grade_data", "speed_grades")
|
|
|
|
bba.pop()
|
|
return bba
|
|
|
|
dev_names = {"25k": "LFE5UM5G-25F", "45k": "LFE5UM5G-45F", "85k": "LFE5UM5G-85F"}
|
|
|
|
def main():
|
|
global max_row, max_col
|
|
pytrellis.load_database(database.get_db_root())
|
|
args = parser.parse_args()
|
|
|
|
# Read port pin file
|
|
with open(args.constids) as f:
|
|
for line in f:
|
|
line = line.replace("(", " ")
|
|
line = line.replace(")", " ")
|
|
line = line.split()
|
|
if len(line) == 0:
|
|
continue
|
|
assert len(line) == 2
|
|
assert line[0] == "X"
|
|
idx = len(constids) + 1
|
|
constids[line[1]] = idx
|
|
|
|
|
|
constids["SLICE"] = constids["TRELLIS_SLICE"]
|
|
constids["PIO"] = constids["TRELLIS_IO"]
|
|
|
|
# print("Initialising chip...")
|
|
chip = pytrellis.Chip(dev_names[args.device])
|
|
# print("Building routing graph...")
|
|
ddrg = pytrellis.make_dedup_chipdb(chip)
|
|
max_row = chip.get_max_row()
|
|
max_col = chip.get_max_col()
|
|
process_timing_data()
|
|
process_pio_db(ddrg, args.device)
|
|
process_loc_globals(chip)
|
|
# print("{} unique location types".format(len(ddrg.locationTypes)))
|
|
bba = write_database(args.device, chip, ddrg, "le")
|
|
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|