79 lines
3.5 KiB
Markdown
79 lines
3.5 KiB
Markdown
## FPGA interchange nextpnr architecture
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This nextpnr architecture is a meta architecture that in theory will implement
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any architecture that emits a complete FPGA interchange device database.
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### FPGA interchange
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The FPGA interchange is a set of file formats intended to describe any modern
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island based FPGA. It consists of three primary file formats:
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- Device database
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- This is a description of a particular FPGA fabric. This description
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includes placement locations, placement constraints and a complete
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description of the routing fabric.
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- This file will also include timing information once added.
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- Logical netlist
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- This is the output of a synthesis tool. This is equivalent to the
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Yosys JSON format, EDIF, or eblif.
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- As part of future nextpnr development, a frontend will be added that
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takes this format as input.
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- Physical netlist
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- This is the output of a place and route tool. It can describe a clustered
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design, a partially or fully placed design, and a partially or fully
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routed design.
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### Current development status
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This architecture implementation can be compiled in conjunction with a FPGA
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interchange device database, and the outputs from
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`fpga_interchange.nextpnr_emit`, which is part of the
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[python-fpga-interchange](https://github.com/SymbiFlow/python-fpga-interchange/)
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library.
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The current implementation is missing essential features for place and route.
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As these features are added, this implementation will become more useful.
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- [ ] Logical netlist macro expansion is not implemented, meaning that any
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macro primitives are unplaceable. Common macro primitives examples are
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differential IO buffers (IBUFDS) and some LUT RAM (e.g. RAM64X1D).
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- [ ] Timing information is missing from the FPGA interchange device
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database, so it is also currently missing from the FPGA interchange
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architecture. Once timing information is added to the device database
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#### Weaknesses of current implementation
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Initial development on the following features is started, but needs more
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refinement.
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- [ ] BEL validity checking is too expensive. The majority of the runtime
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is currently in the LUT rotation. Profiling, optimization and
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algorithm review is likely required to bring strict legalisation
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runtimes into expected levels.
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- [ ] The router lookahead is disabled by default. Without the lookahead,
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router runtime is terrible. However the current lookahead
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implementation is slow to compute and memory intensive, hence why it is
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disabled by default.
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- [ ] Pseudo pips (e.g. pips that consume BELs and or site resources) and
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pseudo site pips (e.g. site pips that route through BELs) consume site
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wires to indicate that they block some resources. This covers many
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validity check cases, but misses some. In particular, when a pseudo
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pip / pseudo site pip has an implication on the constraint system (e.g.
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LUT on a LUT-RAM BEL), an edge may be allowed incorrectly, resulting
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in an illegal design.
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### FPGA interchange fabrics
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Xilinx 7-series, UltraScale and UltraScale+ fabrics have a
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device database generator, via [RapidWright](https://github.com/Xilinx/RapidWright).
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A Lattice Nexus device database is being worked on, via
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[prjoxide](https://github.com/gatecat/prjoxide).
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### FPGA interchange build system
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Construction of chipdb's is currently integrated into nextpnr's CMake build
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system. See fpga\_interchange/examples/README.md for more details.
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