601 lines
18 KiB
C++
601 lines
18 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <algorithm>
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#include <cmath>
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#include "log.h"
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#include "nextpnr.h"
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#include "placer1.h"
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#include "router1.h"
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#include "util.h"
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#include "gfx.h"
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NEXTPNR_NAMESPACE_BEGIN
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// -----------------------------------------------------------------------
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IdString Arch::belTypeToId(BelType type) const
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{
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if (type == TYPE_ICESTORM_LC)
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return id("ICESTORM_LC");
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if (type == TYPE_ICESTORM_RAM)
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return id("ICESTORM_RAM");
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if (type == TYPE_SB_IO)
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return id("SB_IO");
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if (type == TYPE_SB_GB)
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return id("SB_GB");
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if (type == TYPE_ICESTORM_PLL)
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return id("ICESTORM_PLL");
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if (type == TYPE_SB_WARMBOOT)
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return id("SB_WARMBOOT");
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if (type == TYPE_SB_MAC16)
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return id("SB_MAC16");
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if (type == TYPE_ICESTORM_HFOSC)
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return id("ICESTORM_HFOSC");
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if (type == TYPE_ICESTORM_LFOSC)
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return id("ICESTORM_LFOSC");
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if (type == TYPE_SB_I2C)
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return id("SB_I2C");
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if (type == TYPE_SB_SPI)
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return id("SB_SPI");
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if (type == TYPE_IO_I3C)
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return id("IO_I3C");
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if (type == TYPE_SB_LEDDA_IP)
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return id("SB_LEDDA_IP");
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if (type == TYPE_SB_RGBA_DRV)
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return id("SB_RGBA_DRV");
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if (type == TYPE_ICESTORM_SPRAM)
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return id("ICESTORM_SPRAM");
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return IdString();
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}
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BelType Arch::belTypeFromId(IdString type) const
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{
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if (type == id("ICESTORM_LC"))
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return TYPE_ICESTORM_LC;
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if (type == id("ICESTORM_RAM"))
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return TYPE_ICESTORM_RAM;
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if (type == id("SB_IO"))
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return TYPE_SB_IO;
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if (type == id("SB_GB"))
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return TYPE_SB_GB;
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if (type == id("ICESTORM_PLL"))
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return TYPE_ICESTORM_PLL;
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if (type == id("SB_WARMBOOT"))
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return TYPE_SB_WARMBOOT;
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if (type == id("SB_MAC16"))
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return TYPE_SB_MAC16;
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if (type == id("ICESTORM_HFOSC"))
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return TYPE_ICESTORM_HFOSC;
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if (type == id("ICESTORM_LFOSC"))
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return TYPE_ICESTORM_LFOSC;
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if (type == id("SB_I2C"))
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return TYPE_SB_I2C;
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if (type == id("SB_SPI"))
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return TYPE_SB_SPI;
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if (type == id("IO_I3C"))
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return TYPE_IO_I3C;
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if (type == id("SB_LEDDA_IP"))
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return TYPE_SB_LEDDA_IP;
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if (type == id("SB_RGBA_DRV"))
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return TYPE_SB_RGBA_DRV;
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if (type == id("ICESTORM_SPRAM"))
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return TYPE_ICESTORM_SPRAM;
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return TYPE_NONE;
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}
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// -----------------------------------------------------------------------
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void IdString::initialize_arch(const BaseCtx *ctx)
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{
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#define X(t) initialize_add(ctx, #t, PIN_##t);
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#include "portpins.inc"
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#undef X
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}
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IdString Arch::portPinToId(PortPin type) const
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{
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IdString ret;
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if (type > 0 && type < PIN_MAXIDX)
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ret.index = type;
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return ret;
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}
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PortPin Arch::portPinFromId(IdString type) const
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{
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if (type.index > 0 && type.index < PIN_MAXIDX)
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return PortPin(type.index);
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return PIN_NONE;
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}
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// -----------------------------------------------------------------------
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static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
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#if defined(_MSC_VER)
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void load_chipdb();
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#endif
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Arch::Arch(ArchArgs args) : args(args)
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{
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#if defined(_MSC_VER)
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load_chipdb();
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#endif
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#ifdef ICE40_HX1K_ONLY
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if (args.type == ArchArgs::HX1K) {
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chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
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} else {
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log_error("Unsupported iCE40 chip type.\n");
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}
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#else
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if (args.type == ArchArgs::LP384) {
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chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_384));
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} else if (args.type == ArchArgs::LP1K || args.type == ArchArgs::HX1K) {
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chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
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} else if (args.type == ArchArgs::UP5K) {
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chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_5k));
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} else if (args.type == ArchArgs::LP8K || args.type == ArchArgs::HX8K) {
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chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_8k));
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} else {
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log_error("Unsupported iCE40 chip type.\n");
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}
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#endif
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package_info = nullptr;
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for (int i = 0; i < chip_info->num_packages; i++) {
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if (chip_info->packages_data[i].name.get() == args.package) {
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package_info = &(chip_info->packages_data[i]);
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break;
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}
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}
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if (package_info == nullptr)
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log_error("Unsupported package '%s'.\n", args.package.c_str());
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bel_to_cell.resize(chip_info->num_bels);
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wire_to_net.resize(chip_info->num_wires);
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pip_to_net.resize(chip_info->num_pips);
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switches_locked.resize(chip_info->num_switches);
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// Initialise regularly used IDStrings for performance
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id_glb_buf_out = id("GLOBAL_BUFFER_OUTPUT");
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id_icestorm_lc = id("ICESTORM_LC");
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id_sb_io = id("SB_IO");
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id_sb_gb = id("SB_GB");
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id_cen = id("CEN");
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id_clk = id("CLK");
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id_sr = id("SR");
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id_i0 = id("I0");
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id_i1 = id("I1");
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id_i2 = id("I2");
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id_i3 = id("I3");
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id_dff_en = id("DFF_ENABLE");
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id_neg_clk = id("NEG_CLK");
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}
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// -----------------------------------------------------------------------
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std::string Arch::getChipName()
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{
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#ifdef ICE40_HX1K_ONLY
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if (args.type == ArchArgs::HX1K) {
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return "Lattice LP1K";
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} else {
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log_error("Unsupported iCE40 chip type.\n");
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}
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#else
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if (args.type == ArchArgs::LP384) {
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return "Lattice LP384";
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} else if (args.type == ArchArgs::LP1K) {
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return "Lattice LP1K";
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} else if (args.type == ArchArgs::HX1K) {
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return "Lattice HX1K";
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} else if (args.type == ArchArgs::UP5K) {
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return "Lattice UP5K";
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} else if (args.type == ArchArgs::LP8K) {
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return "Lattice LP8K";
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} else if (args.type == ArchArgs::HX8K) {
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return "Lattice HX8K";
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} else {
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log_error("Unknown chip\n");
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}
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#endif
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}
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// -----------------------------------------------------------------------
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IdString Arch::archArgsToId(ArchArgs args) const
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{
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if (args.type == ArchArgs::LP384)
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return id("lp384");
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if (args.type == ArchArgs::LP1K)
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return id("lp1k");
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if (args.type == ArchArgs::HX1K)
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return id("hx1k");
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if (args.type == ArchArgs::UP5K)
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return id("up5k");
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if (args.type == ArchArgs::LP8K)
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return id("lp8k");
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if (args.type == ArchArgs::HX8K)
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return id("hx8k");
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return IdString();
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}
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// -----------------------------------------------------------------------
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BelId Arch::getBelByName(IdString name) const
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{
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BelId ret;
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if (bel_by_name.empty()) {
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for (int i = 0; i < chip_info->num_bels; i++)
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bel_by_name[id(chip_info->bel_data[i].name.get())] = i;
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}
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auto it = bel_by_name.find(name);
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if (it != bel_by_name.end())
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ret.index = it->second;
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return ret;
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}
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BelRange Arch::getBelsAtSameTile(BelId bel) const
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{
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BelRange br;
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NPNR_ASSERT(bel != BelId());
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// This requires Bels at the same tile are consecutive
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int x = chip_info->bel_data[bel.index].x;
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int y = chip_info->bel_data[bel.index].y;
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int start = bel.index, end = bel.index;
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while (start >= 0 && chip_info->bel_data[start].x == x && chip_info->bel_data[start].y == y)
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start--;
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start++;
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br.b.cursor = start;
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while (end < chip_info->num_bels && chip_info->bel_data[end].x == x && chip_info->bel_data[end].y == y)
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end++;
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br.e.cursor = end;
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return br;
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}
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WireId Arch::getWireBelPin(BelId bel, PortPin pin) const
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{
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WireId ret;
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NPNR_ASSERT(bel != BelId());
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int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
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const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
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for (int i = 0; i < num_bel_wires; i++)
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if (bel_wires[i].port == pin) {
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ret.index = bel_wires[i].wire_index;
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break;
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}
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return ret;
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}
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// -----------------------------------------------------------------------
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WireId Arch::getWireByName(IdString name) const
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{
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WireId ret;
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if (wire_by_name.empty()) {
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for (int i = 0; i < chip_info->num_wires; i++)
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wire_by_name[id(chip_info->wire_data[i].name.get())] = i;
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}
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auto it = wire_by_name.find(name);
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if (it != wire_by_name.end())
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ret.index = it->second;
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return ret;
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}
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// -----------------------------------------------------------------------
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PipId Arch::getPipByName(IdString name) const
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{
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PipId ret;
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if (pip_by_name.empty()) {
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for (int i = 0; i < chip_info->num_pips; i++) {
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PipId pip;
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pip.index = i;
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pip_by_name[getPipName(pip)] = i;
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}
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}
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auto it = pip_by_name.find(name);
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if (it != pip_by_name.end())
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ret.index = it->second;
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return ret;
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}
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IdString Arch::getPipName(PipId pip) const
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{
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NPNR_ASSERT(pip != PipId());
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int x = chip_info->pip_data[pip.index].x;
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int y = chip_info->pip_data[pip.index].y;
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std::string src_name = chip_info->wire_data[chip_info->pip_data[pip.index].src].name.get();
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std::replace(src_name.begin(), src_name.end(), '/', '.');
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std::string dst_name = chip_info->wire_data[chip_info->pip_data[pip.index].dst].name.get();
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std::replace(dst_name.begin(), dst_name.end(), '/', '.');
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return id("X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" + src_name + ".->." + dst_name);
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}
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// -----------------------------------------------------------------------
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BelId Arch::getPackagePinBel(const std::string &pin) const
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{
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for (int i = 0; i < package_info->num_pins; i++) {
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if (package_info->pins[i].name.get() == pin) {
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BelId id;
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id.index = package_info->pins[i].bel_index;
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return id;
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}
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}
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return BelId();
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}
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std::string Arch::getBelPackagePin(BelId bel) const
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{
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for (int i = 0; i < package_info->num_pins; i++) {
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if (package_info->pins[i].bel_index == bel.index) {
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return std::string(package_info->pins[i].name.get());
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}
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}
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return "";
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}
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// -----------------------------------------------------------------------
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void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const
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{
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NPNR_ASSERT(bel != BelId());
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x = chip_info->bel_data[bel.index].x;
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y = chip_info->bel_data[bel.index].y;
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gb = chip_info->bel_data[bel.index].type == TYPE_SB_GB;
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}
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delay_t Arch::estimateDelay(WireId src, WireId dst) const
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{
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NPNR_ASSERT(src != WireId());
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int x1 = chip_info->wire_data[src.index].x;
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int y1 = chip_info->wire_data[src.index].y;
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NPNR_ASSERT(dst != WireId());
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int x2 = chip_info->wire_data[dst.index].x;
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int y2 = chip_info->wire_data[dst.index].y;
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int xd = x2 - x1, yd = y2 - y1;
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int xscale = 120, yscale = 120, offset = 0;
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// if (chip_info->wire_data[src.index].type == WIRE_TYPE_SP4_VERT) {
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// yd = yd < -4 ? yd + 4 : (yd < 0 ? 0 : yd);
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// offset = 500;
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// }
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return xscale * abs(xd) + yscale * abs(yd) + offset;
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}
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// -----------------------------------------------------------------------
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bool Arch::place()
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{
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return placer1(getCtx());
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}
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bool Arch::route()
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{
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return router1(getCtx());
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}
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// -----------------------------------------------------------------------
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DecalXY Arch::getFrameDecal() const
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{
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DecalXY decalxy;
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decalxy.decal.type = 'f';
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return decalxy;
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}
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DecalXY Arch::getBelDecal(BelId bel) const
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{
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DecalXY decalxy;
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decalxy.decal.type = 'b';
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decalxy.decal.z = bel.index;
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return decalxy;
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}
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DecalXY Arch::getWireDecal(WireId wire) const
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{
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DecalXY decalxy;
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return decalxy;
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}
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DecalXY Arch::getPipDecal(PipId pip) const
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{
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DecalXY decalxy;
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return decalxy;
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};
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std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
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{
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std::vector<GraphicElement> ret;
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if (decal.type == 'f')
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{
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for (int x = 0; x <= chip_info->width; x++)
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for (int y = 0; y <= chip_info->height; y++) {
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GraphicElement el;
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el.type = GraphicElement::G_LINE;
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el.x1 = x - 0.05, el.x2 = x + 0.05, el.y1 = y, el.y2 = y, el.z = 0;
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ret.push_back(el);
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el.x1 = x, el.x2 = x, el.y1 = y - 0.05, el.y2 = y + 0.05, el.z = 0;
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ret.push_back(el);
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}
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}
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if (decal.type == 'b')
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{
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BelId bel;
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bel.index = decal.z;
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auto bel_type = getBelType(bel);
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if (bel_type == TYPE_ICESTORM_LC) {
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GraphicElement el;
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el.type = GraphicElement::G_BOX;
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el.x1 = chip_info->bel_data[bel.index].x + logic_cell_x1;
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el.x2 = chip_info->bel_data[bel.index].x + logic_cell_x2;
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el.y1 = chip_info->bel_data[bel.index].y + logic_cell_y1 + (chip_info->bel_data[bel.index].z) * logic_cell_pitch;
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el.y2 = chip_info->bel_data[bel.index].y + logic_cell_y2 + (chip_info->bel_data[bel.index].z) * logic_cell_pitch;
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el.z = 0;
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ret.push_back(el);
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if (chip_info->bel_data[bel.index].z == 0) {
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int tx = chip_info->bel_data[bel.index].x;
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int ty = chip_info->bel_data[bel.index].y;
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// Main switchbox
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GraphicElement main_sw;
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main_sw.type = GraphicElement::G_BOX;
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main_sw.x1 = tx + main_swbox_x1;
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main_sw.x2 = tx + main_swbox_x2;
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main_sw.y1 = ty + main_swbox_y1;
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main_sw.y2 = ty + main_swbox_y2;
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ret.push_back(main_sw);
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// Local tracks to LUT input switchbox
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GraphicElement local_sw;
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local_sw.type = GraphicElement::G_BOX;
|
|
local_sw.x1 = tx + local_swbox_x1;
|
|
local_sw.x2 = tx + local_swbox_x2;
|
|
local_sw.y1 = ty + local_swbox_y1;
|
|
local_sw.y2 = ty + local_swbox_y2;
|
|
local_sw.z = 0;
|
|
ret.push_back(local_sw);
|
|
|
|
// All the wires
|
|
for (int i = TILE_WIRE_GLB2LOCAL_0; i <= TILE_WIRE_SP12_H_L_23; i++)
|
|
gfxTileWire(ret, tx, ty, GfxTileWireId(i));
|
|
}
|
|
}
|
|
|
|
if (bel_type == TYPE_SB_IO) {
|
|
if (chip_info->bel_data[bel.index].x == 0 || chip_info->bel_data[bel.index].x == chip_info->width - 1) {
|
|
GraphicElement el;
|
|
el.type = GraphicElement::G_BOX;
|
|
el.x1 = chip_info->bel_data[bel.index].x + 0.1;
|
|
el.x2 = chip_info->bel_data[bel.index].x + 0.9;
|
|
if (chip_info->bel_data[bel.index].z == 0) {
|
|
el.y1 = chip_info->bel_data[bel.index].y + 0.10;
|
|
el.y2 = chip_info->bel_data[bel.index].y + 0.45;
|
|
} else {
|
|
el.y1 = chip_info->bel_data[bel.index].y + 0.55;
|
|
el.y2 = chip_info->bel_data[bel.index].y + 0.90;
|
|
}
|
|
el.z = 0;
|
|
ret.push_back(el);
|
|
} else {
|
|
GraphicElement el;
|
|
el.type = GraphicElement::G_BOX;
|
|
if (chip_info->bel_data[bel.index].z == 0) {
|
|
el.x1 = chip_info->bel_data[bel.index].x + 0.10;
|
|
el.x2 = chip_info->bel_data[bel.index].x + 0.45;
|
|
} else {
|
|
el.x1 = chip_info->bel_data[bel.index].x + 0.55;
|
|
el.x2 = chip_info->bel_data[bel.index].x + 0.90;
|
|
}
|
|
el.y1 = chip_info->bel_data[bel.index].y + 0.1;
|
|
el.y2 = chip_info->bel_data[bel.index].y + 0.9;
|
|
el.z = 0;
|
|
ret.push_back(el);
|
|
}
|
|
}
|
|
|
|
if (bel_type == TYPE_ICESTORM_RAM) {
|
|
GraphicElement el;
|
|
el.type = GraphicElement::G_BOX;
|
|
el.x1 = chip_info->bel_data[bel.index].x + 0.1;
|
|
el.x2 = chip_info->bel_data[bel.index].x + 0.9;
|
|
el.y1 = chip_info->bel_data[bel.index].y + 0.1;
|
|
el.y2 = chip_info->bel_data[bel.index].y + 1.9;
|
|
el.z = 0;
|
|
ret.push_back(el);
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const
|
|
{
|
|
if (cell->type == id("ICESTORM_LC")) {
|
|
if ((fromPort == id("I0") || fromPort == id("I1") || fromPort == id("I2") || fromPort == id("I3")) &&
|
|
(toPort == id("O") || toPort == id("LO"))) {
|
|
delay = 450;
|
|
return true;
|
|
} else if (fromPort == id("CIN") && toPort == id("COUT")) {
|
|
delay = 120;
|
|
return true;
|
|
} else if (fromPort == id("I1") && toPort == id("COUT")) {
|
|
delay = 260;
|
|
return true;
|
|
} else if (fromPort == id("I2") && toPort == id("COUT")) {
|
|
delay = 230;
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
IdString Arch::getPortClock(const CellInfo *cell, IdString port) const
|
|
{
|
|
if (cell->type == id("ICESTORM_LC") && bool_or_default(cell->params, id("DFF_ENABLE"))) {
|
|
if (port != id("LO") && port != id("CIN") && port != id("COUT"))
|
|
return id("CLK");
|
|
}
|
|
return IdString();
|
|
}
|
|
|
|
bool Arch::isClockPort(const CellInfo *cell, IdString port) const
|
|
{
|
|
if (cell->type == id("ICESTORM_LC") && port == id("CLK"))
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
bool Arch::isGlobalNet(const NetInfo *net) const
|
|
{
|
|
if (net == nullptr)
|
|
return false;
|
|
return net->driver.cell != nullptr && net->driver.port == id_glb_buf_out;
|
|
}
|
|
|
|
NEXTPNR_NAMESPACE_END
|