774 lines
22 KiB
C++
774 lines
22 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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* Copyright (C) 2018 David Shah <david@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef NEXTPNR_H
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#error Include "arch.h" via "nextpnr.h" only.
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#endif
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#include <sstream>
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NEXTPNR_NAMESPACE_BEGIN
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/**** Everything in this section must be kept in sync with chipdb.py ****/
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template <typename T> struct RelPtr
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{
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int32_t offset;
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// void set(const T *ptr) {
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// offset = reinterpret_cast<const char*>(ptr) -
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// reinterpret_cast<const char*>(this);
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// }
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const T *get() const { return reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset); }
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const T &operator[](size_t index) const { return get()[index]; }
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const T &operator*() const { return *(get()); }
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const T *operator->() const { return get(); }
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};
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NPNR_PACKED_STRUCT(struct BelWirePOD {
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LocationPOD rel_wire_loc;
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int32_t wire_index;
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PortPin port;
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});
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NPNR_PACKED_STRUCT(struct BelInfoPOD {
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RelPtr<char> name;
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BelType type;
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int32_t num_bel_wires;
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RelPtr<BelWirePOD> bel_wires;
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});
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NPNR_PACKED_STRUCT(struct BelPortPOD {
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LocationPOD rel_bel_loc;
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int32_t bel_index;
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PortPin port;
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});
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NPNR_PACKED_STRUCT(struct PipInfoPOD {
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LocationPOD rel_src_loc, rel_dst_loc;
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int32_t src_idx, dst_idx;
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int32_t delay;
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int16_t tile_type;
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int8_t pip_type;
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int8_t padding_0;
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});
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NPNR_PACKED_STRUCT(struct PipLocatorPOD {
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LocationPOD rel_loc;
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int32_t index;
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});
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NPNR_PACKED_STRUCT(struct WireInfoPOD {
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RelPtr<char> name;
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int32_t num_uphill, num_downhill;
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RelPtr<PipLocatorPOD> pips_uphill, pips_downhill;
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int32_t num_bels_downhill;
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BelPortPOD bel_uphill;
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RelPtr<BelPortPOD> bels_downhill;
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});
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NPNR_PACKED_STRUCT(struct LocationTypePOD {
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int32_t num_bels, num_wires, num_pips;
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RelPtr<BelInfoPOD> bel_data;
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RelPtr<WireInfoPOD> wire_data;
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RelPtr<PipInfoPOD> pip_data;
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});
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NPNR_PACKED_STRUCT(struct ChipInfoPOD {
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int32_t width, height;
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int32_t num_tiles;
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int32_t num_location_types;
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RelPtr<LocationTypePOD> locations;
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RelPtr<int32_t> location_type;
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RelPtr<RelPtr<char>> tiletype_names;
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});
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#if defined(_MSC_VER)
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extern const char *chipdb_blob_25k;
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extern const char *chipdb_blob_45k;
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extern const char *chipdb_blob_85k;
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#else
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extern const char chipdb_blob_25k[];
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extern const char chipdb_blob_45k[];
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extern const char chipdb_blob_85k[];
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#endif
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/************************ End of chipdb section. ************************/
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struct BelIterator
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{
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const ChipInfoPOD *chip;
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int cursor_index;
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int cursor_tile;
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BelIterator operator++()
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{
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cursor_index++;
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while (cursor_tile < chip->num_tiles &&
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cursor_index >= chip->locations[chip->location_type[cursor_tile]].num_bels) {
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cursor_index = 0;
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cursor_tile++;
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}
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return *this;
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}
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BelIterator operator++(int)
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{
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BelIterator prior(*this);
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++(*this);
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return prior;
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}
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bool operator!=(const BelIterator &other) const
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{
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return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile;
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}
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bool operator==(const BelIterator &other) const
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{
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return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile;
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}
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BelId operator*() const
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{
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BelId ret;
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ret.location.x = cursor_tile % chip->width;
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ret.location.y = cursor_tile / chip->width;
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ret.index = cursor_index;
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return ret;
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}
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};
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struct BelRange
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{
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BelIterator b, e;
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BelIterator begin() const { return b; }
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BelIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct BelPinIterator
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{
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const BelPortPOD *ptr = nullptr;
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Location wire_loc;
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void operator++() { ptr++; }
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bool operator!=(const BelPinIterator &other) const { return ptr != other.ptr; }
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BelPin operator*() const
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{
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BelPin ret;
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ret.bel.index = ptr->bel_index;
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ret.bel.location = wire_loc + ptr->rel_bel_loc;
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ret.pin = ptr->port;
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return ret;
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}
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};
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struct BelPinRange
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{
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BelPinIterator b, e;
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BelPinIterator begin() const { return b; }
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BelPinIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct WireIterator
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{
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const ChipInfoPOD *chip;
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int cursor_index;
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int cursor_tile;
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WireIterator operator++()
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{
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cursor_index++;
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while (cursor_tile < chip->num_tiles &&
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cursor_index >= chip->locations[chip->location_type[cursor_tile]].num_wires) {
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cursor_index = 0;
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cursor_tile++;
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}
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return *this;
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}
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WireIterator operator++(int)
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{
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WireIterator prior(*this);
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++(*this);
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return prior;
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}
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bool operator!=(const WireIterator &other) const
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{
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return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile;
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}
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bool operator==(const WireIterator &other) const
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{
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return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile;
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}
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WireId operator*() const
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{
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WireId ret;
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ret.location.x = cursor_tile % chip->width;
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ret.location.y = cursor_tile / chip->width;
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ret.index = cursor_index;
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return ret;
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}
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};
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struct WireRange
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{
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WireIterator b, e;
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WireIterator begin() const { return b; }
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WireIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct AllPipIterator
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{
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const ChipInfoPOD *chip;
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int cursor_index;
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int cursor_tile;
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AllPipIterator operator++()
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{
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cursor_index++;
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while (cursor_tile < chip->num_tiles &&
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cursor_index >= chip->locations[chip->location_type[cursor_tile]].num_pips) {
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cursor_index = 0;
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cursor_tile++;
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}
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return *this;
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}
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AllPipIterator operator++(int)
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{
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AllPipIterator prior(*this);
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++(*this);
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return prior;
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}
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bool operator!=(const AllPipIterator &other) const
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{
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return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile;
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}
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bool operator==(const AllPipIterator &other) const
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{
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return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile;
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}
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PipId operator*() const
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{
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PipId ret;
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ret.location.x = cursor_tile % chip->width;
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ret.location.y = cursor_tile / chip->width;
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ret.index = cursor_index;
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return ret;
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}
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};
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struct AllPipRange
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{
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AllPipIterator b, e;
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AllPipIterator begin() const { return b; }
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AllPipIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct PipIterator
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{
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const PipLocatorPOD *cursor = nullptr;
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Location wire_loc;
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void operator++() { cursor++; }
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bool operator!=(const PipIterator &other) const { return cursor != other.cursor; }
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PipId operator*() const
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{
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PipId ret;
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ret.index = cursor->index;
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ret.location = wire_loc + cursor->rel_loc;
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return ret;
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}
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};
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struct PipRange
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{
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PipIterator b, e;
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PipIterator begin() const { return b; }
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PipIterator end() const { return e; }
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};
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struct ArchArgs
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{
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enum
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{
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NONE,
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LFE5U_25F,
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LFE5U_45F,
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LFE5U_85F,
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} type = NONE;
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std::string package;
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int speed = 6;
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};
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struct Arch : BaseCtx
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{
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const ChipInfoPOD *chip_info;
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mutable std::unordered_map<IdString, BelId> bel_by_name;
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mutable std::unordered_map<IdString, WireId> wire_by_name;
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mutable std::unordered_map<IdString, PipId> pip_by_name;
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std::unordered_map<BelId, IdString> bel_to_cell;
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std::unordered_map<WireId, IdString> wire_to_net;
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std::unordered_map<PipId, IdString> pip_to_net;
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std::unordered_map<PipId, IdString> switches_locked;
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ArchArgs args;
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Arch(ArchArgs args);
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std::string getChipName();
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IdString archId() const { return id("ecp5"); }
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IdString archArgsToId(ArchArgs args) const;
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IdString belTypeToId(BelType type) const;
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BelType belTypeFromId(IdString id) const;
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IdString portPinToId(PortPin type) const;
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PortPin portPinFromId(IdString id) const;
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// -------------------------------------------------
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BelId getBelByName(IdString name) const;
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template <typename Id> const LocationTypePOD *locInfo(Id &id) const
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{
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return &(chip_info->locations[chip_info->location_type[id.location.y * chip_info->width + id.location.x]]);
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}
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IdString getBelName(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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std::stringstream name;
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name << "X" << bel.location.x << "/Y" << bel.location.y << "/" << locInfo(bel)->bel_data[bel.index].name.get();
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return id(name.str());
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}
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uint32_t getBelChecksum(BelId bel) const { return bel.index; }
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void bindBel(BelId bel, IdString cell, PlaceStrength strength)
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{
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NPNR_ASSERT(bel != BelId());
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NPNR_ASSERT(bel_to_cell[bel] == IdString());
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bel_to_cell[bel] = cell;
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cells[cell]->bel = bel;
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cells[cell]->belStrength = strength;
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}
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void unbindBel(BelId bel)
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{
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NPNR_ASSERT(bel != BelId());
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NPNR_ASSERT(bel_to_cell[bel] != IdString());
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cells[bel_to_cell[bel]]->bel = BelId();
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cells[bel_to_cell[bel]]->belStrength = STRENGTH_NONE;
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bel_to_cell[bel] = IdString();
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}
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bool checkBelAvail(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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return bel_to_cell.find(bel) == bel_to_cell.end() || bel_to_cell.at(bel) == IdString();
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}
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IdString getBoundBelCell(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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if (bel_to_cell.find(bel) == bel_to_cell.end())
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return IdString();
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else
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return bel_to_cell.at(bel);
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}
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IdString getConflictingBelCell(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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if (bel_to_cell.find(bel) == bel_to_cell.end())
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return IdString();
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else
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return bel_to_cell.at(bel);
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}
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BelRange getBels() const
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{
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BelRange range;
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range.b.cursor_tile = 0;
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range.b.cursor_index = -1;
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range.b.chip = chip_info;
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++range.b; //-1 and then ++ deals with the case of no Bels in the first tile
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range.e.cursor_tile = chip_info->width * chip_info->height;
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range.e.cursor_index = 0;
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range.e.chip = chip_info;
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return range;
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}
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BelRange getBelsByType(BelType type) const
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{
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BelRange range;
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// FIXME
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#if 0
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if (type == "TYPE_A") {
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range.b.cursor = bels_type_a_begin;
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range.e.cursor = bels_type_a_end;
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}
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...
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#endif
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return range;
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}
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BelRange getBelsAtSameTile(BelId bel) const;
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BelType getBelType(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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return locInfo(bel)->bel_data[bel.index].type;
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}
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WireId getWireBelPin(BelId bel, PortPin pin) const;
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BelPin getBelPinUphill(WireId wire) const
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{
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BelPin ret;
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NPNR_ASSERT(wire != WireId());
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if (locInfo(wire)->wire_data[wire.index].bel_uphill.bel_index >= 0) {
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ret.bel.index = locInfo(wire)->wire_data[wire.index].bel_uphill.bel_index;
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ret.bel.location = wire.location + locInfo(wire)->wire_data[wire.index].bel_uphill.rel_bel_loc;
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ret.pin = locInfo(wire)->wire_data[wire.index].bel_uphill.port;
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}
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return ret;
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}
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BelPinRange getBelPinsDownhill(WireId wire) const
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{
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BelPinRange range;
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NPNR_ASSERT(wire != WireId());
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range.b.ptr = locInfo(wire)->wire_data[wire.index].bels_downhill.get();
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range.b.wire_loc = wire.location;
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range.e.ptr = range.b.ptr + locInfo(wire)->wire_data[wire.index].num_bels_downhill;
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range.e.wire_loc = wire.location;
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return range;
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}
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// -------------------------------------------------
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WireId getWireByName(IdString name) const;
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IdString getWireName(WireId wire) const
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{
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NPNR_ASSERT(wire != WireId());
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std::stringstream name;
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name << "X" << wire.location.x << "/Y" << wire.location.y << "/"
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<< locInfo(wire)->wire_data[wire.index].name.get();
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return id(name.str());
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}
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uint32_t getWireChecksum(WireId wire) const { return wire.index; }
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void bindWire(WireId wire, IdString net, PlaceStrength strength)
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{
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NPNR_ASSERT(wire != WireId());
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NPNR_ASSERT(wire_to_net[wire] == IdString());
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wire_to_net[wire] = net;
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nets[net]->wires[wire].pip = PipId();
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nets[net]->wires[wire].strength = strength;
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}
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void unbindWire(WireId wire)
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{
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NPNR_ASSERT(wire != WireId());
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NPNR_ASSERT(wire_to_net[wire] != IdString());
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auto &net_wires = nets[wire_to_net[wire]]->wires;
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auto it = net_wires.find(wire);
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NPNR_ASSERT(it != net_wires.end());
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auto pip = it->second.pip;
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if (pip != PipId()) {
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pip_to_net[pip] = IdString();
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}
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net_wires.erase(it);
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wire_to_net[wire] = IdString();
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}
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bool checkWireAvail(WireId wire) const
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{
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NPNR_ASSERT(wire != WireId());
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return wire_to_net.find(wire) == wire_to_net.end() || wire_to_net.at(wire) == IdString();
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}
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IdString getBoundWireNet(WireId wire) const
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{
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NPNR_ASSERT(wire != WireId());
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if (wire_to_net.find(wire) == wire_to_net.end())
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return IdString();
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else
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return wire_to_net.at(wire);
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}
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IdString getConflictingWireNet(WireId wire) const
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{
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NPNR_ASSERT(wire != WireId());
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if (wire_to_net.find(wire) == wire_to_net.end())
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return IdString();
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else
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return wire_to_net.at(wire);
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}
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WireRange getWires() const
|
|
{
|
|
WireRange range;
|
|
range.b.cursor_tile = 0;
|
|
range.b.cursor_index = -1;
|
|
range.b.chip = chip_info;
|
|
++range.b; //-1 and then ++ deals with the case of no wries in the first tile
|
|
range.e.cursor_tile = chip_info->width * chip_info->height;
|
|
range.e.cursor_index = 0;
|
|
range.e.chip = chip_info;
|
|
return range;
|
|
}
|
|
|
|
// -------------------------------------------------
|
|
|
|
PipId getPipByName(IdString name) const;
|
|
IdString getPipName(PipId pip) const;
|
|
|
|
uint32_t getPipChecksum(PipId pip) const { return pip.index; }
|
|
|
|
void bindPip(PipId pip, IdString net, PlaceStrength strength)
|
|
{
|
|
NPNR_ASSERT(pip != PipId());
|
|
NPNR_ASSERT(pip_to_net[pip] == IdString());
|
|
|
|
pip_to_net[pip] = net;
|
|
|
|
WireId dst;
|
|
dst.index = locInfo(pip)->pip_data[pip.index].dst_idx;
|
|
dst.location = pip.location + locInfo(pip)->pip_data[pip.index].rel_dst_loc;
|
|
NPNR_ASSERT(wire_to_net[dst] == IdString());
|
|
wire_to_net[dst] = net;
|
|
nets[net]->wires[dst].pip = pip;
|
|
nets[net]->wires[dst].strength = strength;
|
|
}
|
|
|
|
void unbindPip(PipId pip)
|
|
{
|
|
NPNR_ASSERT(pip != PipId());
|
|
NPNR_ASSERT(pip_to_net[pip] != IdString());
|
|
|
|
WireId dst;
|
|
dst.index = locInfo(pip)->pip_data[pip.index].dst_idx;
|
|
dst.location = pip.location + locInfo(pip)->pip_data[pip.index].rel_dst_loc;
|
|
NPNR_ASSERT(wire_to_net[dst] != IdString());
|
|
wire_to_net[dst] = IdString();
|
|
nets[pip_to_net[pip]]->wires.erase(dst);
|
|
|
|
pip_to_net[pip] = IdString();
|
|
}
|
|
|
|
bool checkPipAvail(PipId pip) const
|
|
{
|
|
NPNR_ASSERT(pip != PipId());
|
|
return pip_to_net.find(pip) == pip_to_net.end() || pip_to_net.at(pip) == IdString();
|
|
}
|
|
|
|
IdString getBoundPipNet(PipId pip) const
|
|
{
|
|
NPNR_ASSERT(pip != PipId());
|
|
if (pip_to_net.find(pip) == pip_to_net.end())
|
|
return IdString();
|
|
else
|
|
return pip_to_net.at(pip);
|
|
}
|
|
|
|
IdString getConflictingPipNet(PipId pip) const
|
|
{
|
|
NPNR_ASSERT(pip != PipId());
|
|
if (pip_to_net.find(pip) == pip_to_net.end())
|
|
return IdString();
|
|
else
|
|
return pip_to_net.at(pip);
|
|
}
|
|
|
|
AllPipRange getPips() const
|
|
{
|
|
AllPipRange range;
|
|
range.b.cursor_tile = 0;
|
|
range.b.cursor_index = -1;
|
|
range.b.chip = chip_info;
|
|
++range.b; //-1 and then ++ deals with the case of no wries in the first tile
|
|
range.e.cursor_tile = chip_info->width * chip_info->height;
|
|
range.e.cursor_index = 0;
|
|
range.e.chip = chip_info;
|
|
return range;
|
|
}
|
|
|
|
WireId getPipSrcWire(PipId pip) const
|
|
{
|
|
WireId wire;
|
|
NPNR_ASSERT(pip != PipId());
|
|
wire.index = locInfo(pip)->pip_data[pip.index].src_idx;
|
|
wire.location = pip.location + locInfo(pip)->pip_data[pip.index].rel_src_loc;
|
|
return wire;
|
|
}
|
|
|
|
WireId getPipDstWire(PipId pip) const
|
|
{
|
|
WireId wire;
|
|
NPNR_ASSERT(pip != PipId());
|
|
wire.index = locInfo(pip)->pip_data[pip.index].dst_idx;
|
|
wire.location = pip.location + locInfo(pip)->pip_data[pip.index].rel_dst_loc;
|
|
return wire;
|
|
}
|
|
|
|
DelayInfo getPipDelay(PipId pip) const
|
|
{
|
|
DelayInfo delay;
|
|
NPNR_ASSERT(pip != PipId());
|
|
delay.delay = locInfo(pip)->pip_data[pip.index].delay;
|
|
return delay;
|
|
}
|
|
|
|
PipRange getPipsDownhill(WireId wire) const
|
|
{
|
|
PipRange range;
|
|
NPNR_ASSERT(wire != WireId());
|
|
range.b.cursor = locInfo(wire)->wire_data[wire.index].pips_downhill.get();
|
|
range.b.wire_loc = wire.location;
|
|
range.e.cursor = range.b.cursor + locInfo(wire)->wire_data[wire.index].num_downhill;
|
|
range.e.wire_loc = wire.location;
|
|
return range;
|
|
}
|
|
|
|
PipRange getPipsUphill(WireId wire) const
|
|
{
|
|
PipRange range;
|
|
NPNR_ASSERT(wire != WireId());
|
|
range.b.cursor = locInfo(wire)->wire_data[wire.index].pips_uphill.get();
|
|
range.b.wire_loc = wire.location;
|
|
range.e.cursor = range.b.cursor + locInfo(wire)->wire_data[wire.index].num_uphill;
|
|
range.e.wire_loc = wire.location;
|
|
return range;
|
|
}
|
|
|
|
PipRange getWireAliases(WireId wire) const
|
|
{
|
|
PipRange range;
|
|
NPNR_ASSERT(wire != WireId());
|
|
range.b.cursor = nullptr;
|
|
range.e.cursor = nullptr;
|
|
return range;
|
|
}
|
|
|
|
std::string getPipTiletype(PipId pip) const
|
|
{
|
|
return chip_info->tiletype_names[locInfo(pip)->pip_data[pip.index].tile_type].get();
|
|
}
|
|
|
|
int8_t getPipType(PipId pip) const { return locInfo(pip)->pip_data[pip.index].pip_type; }
|
|
|
|
BelId getPackagePinBel(const std::string &pin) const;
|
|
std::string getBelPackagePin(BelId bel) const;
|
|
|
|
// -------------------------------------------------
|
|
|
|
GroupId getGroupByName(IdString name) const { return GroupId(); }
|
|
IdString getGroupName(GroupId group) const { return IdString(); }
|
|
std::vector<GroupId> getGroups() const { return std::vector<GroupId>(); }
|
|
std::vector<BelId> getGroupBels(GroupId group) const { return std::vector<BelId>(); }
|
|
std::vector<WireId> getGroupWires(GroupId group) const { return std::vector<WireId>(); }
|
|
std::vector<PipId> getGroupPips(GroupId group) const { return std::vector<PipId>(); }
|
|
std::vector<GroupId> getGroupGroups(GroupId group) const { return std::vector<GroupId>(); }
|
|
|
|
// -------------------------------------------------
|
|
|
|
void estimatePosition(BelId bel, int &x, int &y, bool &gb) const;
|
|
delay_t estimateDelay(WireId src, WireId dst) const;
|
|
delay_t getDelayEpsilon() const { return 20; }
|
|
delay_t getRipupDelayPenalty() const { return 200; }
|
|
float getDelayNS(delay_t v) const { return v * 0.001; }
|
|
uint32_t getDelayChecksum(delay_t v) const { return v; }
|
|
|
|
// -------------------------------------------------
|
|
|
|
bool pack();
|
|
bool place();
|
|
bool route();
|
|
|
|
// -------------------------------------------------
|
|
|
|
std::vector<GraphicElement> getDecalGraphics(DecalId decal) const;
|
|
|
|
DecalXY getFrameDecal() const;
|
|
DecalXY getBelDecal(BelId bel) const;
|
|
DecalXY getWireDecal(WireId wire) const;
|
|
DecalXY getPipDecal(PipId pip) const;
|
|
DecalXY getGroupDecal(GroupId group) const;
|
|
|
|
// -------------------------------------------------
|
|
|
|
// Get the delay through a cell from one port to another, returning false
|
|
// if no path exists
|
|
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const;
|
|
// Get the associated clock to a port, or empty if the port is combinational
|
|
IdString getPortClock(const CellInfo *cell, IdString port) const;
|
|
// Return true if a port is a clock
|
|
bool isClockPort(const CellInfo *cell, IdString port) const;
|
|
// Return true if a port is a net
|
|
bool isGlobalNet(const NetInfo *net) const;
|
|
|
|
// -------------------------------------------------
|
|
// Placement validity checks
|
|
bool isValidBelForCell(CellInfo *cell, BelId bel) const;
|
|
bool isBelLocationValid(BelId bel) const;
|
|
|
|
// Helper function for above
|
|
bool slicesCompatible(const std::vector<const CellInfo *> &cells) const;
|
|
|
|
IdString id_trellis_slice;
|
|
IdString id_clk, id_lsr;
|
|
IdString id_clkmux, id_lsrmux;
|
|
IdString id_srmode, id_mode;
|
|
};
|
|
|
|
NEXTPNR_NAMESPACE_END
|