2e8280a949
It seems that the internal registers on the BSRAM output pins in READ_MODE=1'b1 (pipeline) mode do not function properly because in the images generated by Gowin IDE an external register is added to each pin, and the BSRAM itself switches to READ_MODE=1'b0 (bypass) mode . This is observed on Tangnano9k and Tangnano20k boards. Here we repeat this fix. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
260 lines
8.6 KiB
C++
260 lines
8.6 KiB
C++
#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
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#include "himbaechel_constids.h"
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#include "himbaechel_helpers.h"
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#include "gowin.h"
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#include "gowin_utils.h"
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NEXTPNR_NAMESPACE_BEGIN
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// tile extra data
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IdString GowinUtils::get_tile_class(int x, int y)
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{
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int tile = tile_by_xy(ctx->chip_info, x, y);
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const Tile_extra_data_POD *extra =
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reinterpret_cast<const Tile_extra_data_POD *>(chip_tile_info(ctx->chip_info, tile).extra_data.get());
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return IdString(extra->class_id);
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}
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// oser16/ides16 aux cell offsets
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Loc GowinUtils::get_tile_io16_offs(int x, int y)
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{
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int tile = tile_by_xy(ctx->chip_info, x, y);
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const Tile_extra_data_POD *extra =
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reinterpret_cast<const Tile_extra_data_POD *>(chip_tile_info(ctx->chip_info, tile).extra_data.get());
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return Loc(extra->io16_x_off, extra->io16_y_off, 0);
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}
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// pin functions: GCLKT_4, SSPI_CS, READY etc
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IdStringList GowinUtils::get_pin_funcs(BelId io_bel)
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{
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IdStringList bel_name = ctx->getBelName(io_bel);
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const PadInfoPOD *pins = ctx->package_info->pads.get();
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size_t len = ctx->package_info->pads.ssize();
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for (size_t i = 0; i < len; i++) {
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const PadInfoPOD *pin = &pins[i];
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if (IdString(pin->tile) == bel_name[0] && IdString(pin->bel) == bel_name[1]) {
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return IdStringList::parse(ctx, IdString(pin->pad_function).str(ctx));
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}
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}
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return IdStringList();
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}
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// PLL pads
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BelId GowinUtils::get_pll_bel(BelId io_bel, IdString type)
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{
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IdStringList bel_name = ctx->getBelName(io_bel);
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const PadInfoPOD *pins = ctx->package_info->pads.get();
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size_t len = ctx->package_info->pads.ssize();
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for (size_t i = 0; i < len; i++) {
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const PadInfoPOD *pin = &pins[i];
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if (IdString(pin->tile) == bel_name[0] && IdString(pin->bel) == bel_name[1]) {
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const Pad_extra_data_POD *extra = reinterpret_cast<const Pad_extra_data_POD *>(pin->extra_data.get());
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if (extra != nullptr && IdString(extra->pll_type) == type) {
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return ctx->getBelByName(IdStringList::concat(IdString(extra->pll_tile), IdString(extra->pll_bel)));
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}
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}
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}
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return BelId();
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}
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bool GowinUtils::is_simple_io_bel(BelId bel)
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{
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return chip_bel_info(ctx->chip_info, bel).flags & BelFlags::FLAG_SIMPLE_IO;
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}
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Loc GowinUtils::get_pair_iologic_bel(Loc loc)
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{
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int const z[] = {1, 0, 3, 2};
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loc.z = BelZ::IOLOGICA_Z + z[(loc.z - BelZ::IOLOGICA_Z)];
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return loc;
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}
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BelId GowinUtils::get_io_bel_from_iologic(BelId bel)
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{
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Loc loc = ctx->getBelLocation(bel);
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loc.z = BelZ::IOBA_Z + ((loc.z - BelZ::IOLOGICA_Z) & 1);
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return ctx->getBelByLocation(loc);
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}
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bool GowinUtils::is_diff_io_supported(IdString type)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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for (auto &dtype : extra->diff_io_types) {
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if (IdString(dtype) == type) {
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return true;
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}
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}
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return false;
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}
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bool GowinUtils::have_bottom_io_cnds(void)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return extra->bottom_io.conditions.size() != 0;
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}
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IdString GowinUtils::get_bottom_io_wire_a_net(int8_t condition)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return IdString(extra->bottom_io.conditions[condition].wire_a_net);
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}
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IdString GowinUtils::get_bottom_io_wire_b_net(int8_t condition)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return IdString(extra->bottom_io.conditions[condition].wire_b_net);
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}
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bool GowinUtils::have_SP32(void)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return extra->chip_flags & Extra_chip_data_POD::HAS_SP32;
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}
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bool GowinUtils::need_SP_fix(void)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return extra->chip_flags & Extra_chip_data_POD::NEED_SP_FIX;
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}
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bool GowinUtils::need_BSRAM_OUTREG_fix(void)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return extra->chip_flags & Extra_chip_data_POD::NEED_BSRAM_OUTREG_FIX;
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}
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std::unique_ptr<CellInfo> GowinUtils::create_cell(IdString name, IdString type)
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{
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NPNR_ASSERT(!ctx->cells.count(name));
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return std::make_unique<CellInfo>(ctx, name, type);
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}
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// DSP
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Loc GowinUtils::get_dsp_next_9_in_chain(Loc from) const
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{
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Loc res;
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res.y = from.y;
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if (get_dsp_18_idx(from.z) == 0) {
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res.x = from.x;
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res.z = from.z + 4;
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return res;
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}
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if (get_dsp_macro_num(from.z)) {
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// next DSP
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res.x = from.x + 9;
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res.z = from.z & (~0x24);
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} else {
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// next macro
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res.x = from.x;
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res.z = get_dsp_next_macro(from.z) & (~4);
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}
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return res;
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}
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Loc GowinUtils::get_dsp_next_macro_in_chain(Loc from) const
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{
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Loc res;
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res.y = from.y;
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if (get_dsp_macro_num(from.z)) {
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// next DSP
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res.x = from.x + 9;
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res.z = from.z & (~0x20);
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} else {
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// next macro
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res.x = from.x;
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res.z = get_dsp_next_macro(from.z);
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}
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return res;
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}
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Loc GowinUtils::get_dsp_next_in_chain(Loc from, IdString dsp_type) const
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{
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if (dsp_type.in(id_PADD9, id_PADD18, id_MULT9X9, id_MULT18X18)) {
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return get_dsp_next_9_in_chain(from);
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}
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if (dsp_type.in(id_ALU54D, id_MULTALU18X18, id_MULTALU36X18, id_MULTADDALU18X18)) {
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return get_dsp_next_macro_in_chain(from);
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}
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NPNR_ASSERT_FALSE("Unknown DSP cell type.");
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}
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CellInfo *GowinUtils::dsp_bus_src(const CellInfo *ci, const char *bus_prefix, int wire_num) const
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{
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bool connected_to_const = false; // and disconnected too
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CellInfo *connected_to_cell = nullptr;
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for (int i = 0; i < wire_num; ++i) {
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const NetInfo *net = ci->getPort(ctx->idf("%s[%d]", bus_prefix, i));
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if (connected_to_cell == nullptr) {
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if (net == nullptr || net->driver.cell == nullptr || net->name == ctx->id("$PACKER_VCC") ||
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net->name == ctx->id("$PACKER_GND")) {
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connected_to_const = true;
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continue;
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} else {
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if (connected_to_const) {
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log_error("The %s cell %s bus is connected simultaneously to constants and to another DSP.\n",
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ctx->nameOf(ci), bus_prefix);
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}
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}
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}
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if (net == nullptr || !is_dsp(net->driver.cell)) {
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log_error("The %s cell %s bus is not connected to another DSP.\n", ctx->nameOf(ci), bus_prefix);
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}
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if (connected_to_cell != nullptr && net->driver.cell != connected_to_cell) {
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log_error("The %s cell %s bus is connected to different DSPs: %s and %s.\n", ctx->nameOf(ci), bus_prefix,
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ctx->nameOf(connected_to_cell), ctx->nameOf(net->driver.cell));
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}
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connected_to_cell = net->driver.cell;
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}
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if (connected_to_const) {
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return nullptr;
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}
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return connected_to_cell;
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}
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CellInfo *GowinUtils::dsp_bus_dst(const CellInfo *ci, const char *bus_prefix, int wire_num) const
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{
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bool disconnected = false; // and disconnected too
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CellInfo *connected_to_cell = nullptr;
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for (int i = 0; i < wire_num; ++i) {
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const NetInfo *net = ci->getPort(ctx->idf("%s[%d]", bus_prefix, i));
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if (connected_to_cell == nullptr) {
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if (net == nullptr || net->users.entries() == 0) {
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disconnected = true;
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continue;
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} else {
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if (disconnected) {
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log_error("The %s cell %s bus is partially disconnected.\n", ctx->nameOf(ci), bus_prefix);
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}
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}
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}
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if (net->users.entries() > 1) {
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log_error("Net %s has >1 users.\n", ctx->nameOf(net));
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}
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CellInfo *dst = (*net->users.begin()).cell;
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if (net == nullptr || !is_dsp(dst)) {
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log_error("The %s cell %s bus is not connected to another DSP.\n", ctx->nameOf(ci), bus_prefix);
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}
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if (connected_to_cell != nullptr && dst != connected_to_cell) {
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log_error("The %s cell %s bus is connected to different DSPs: %s and %s.\n", ctx->nameOf(ci), bus_prefix,
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ctx->nameOf(connected_to_cell), ctx->nameOf(dst));
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}
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connected_to_cell = dst;
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}
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if (disconnected) {
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return nullptr;
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}
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return connected_to_cell;
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}
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NEXTPNR_NAMESPACE_END
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