441 lines
19 KiB
C++
441 lines
19 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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* Copyright (C) 2018 David Shah <david@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "bitstream.h"
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#include <vector>
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#include "log.h"
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NEXTPNR_NAMESPACE_BEGIN
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inline TileType tile_at(const Context *ctx, int x, int y)
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{
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return ctx->chip_info->tile_grid[y * ctx->chip_info->width + x];
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}
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const ConfigEntryPOD &find_config(const TileInfoPOD &tile, const std::string &name)
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{
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for (int i = 0; i < tile.num_config_entries; i++) {
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if (std::string(tile.entries[i].name.get()) == name) {
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return tile.entries[i];
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}
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}
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assert(false);
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}
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std::tuple<int8_t, int8_t, int8_t> get_ieren(const BitstreamInfoPOD &bi, int8_t x, int8_t y, int8_t z)
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{
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for (int i = 0; i < bi.num_ierens; i++) {
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auto ie = bi.ierens[i];
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if (ie.iox == x && ie.ioy == y && ie.ioz == z) {
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return std::make_tuple(ie.ierx, ie.iery, ie.ierz);
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}
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}
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// No pin at this location
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return std::make_tuple(-1, -1, -1);
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};
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void set_config(const TileInfoPOD &ti, std::vector<std::vector<int8_t>> &tile_cfg, const std::string &name, bool value,
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int index = -1)
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{
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const ConfigEntryPOD &cfg = find_config(ti, name);
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if (index == -1) {
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for (int i = 0; i < cfg.num_bits; i++) {
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int8_t &cbit = tile_cfg.at(cfg.bits[i].row).at(cfg.bits[i].col);
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if (cbit && !value)
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log_error("clearing already set config bit %s", name.c_str());
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cbit = value;
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}
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} else {
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int8_t &cbit = tile_cfg.at(cfg.bits[index].row).at(cfg.bits[index].col);
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cbit = value;
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if (cbit && !value)
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log_error("clearing already set config bit %s[%d]", name.c_str(), index);
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}
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}
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int get_param_or_def(const CellInfo *cell, const IdString param, int defval = 0)
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{
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auto found = cell->params.find(param);
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if (found != cell->params.end())
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return std::stoi(found->second);
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else
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return defval;
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}
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std::string get_param_str_or_def(const CellInfo *cell, const IdString param, std::string defval = "")
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{
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auto found = cell->params.find(param);
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if (found != cell->params.end())
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return found->second;
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else
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return defval;
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}
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char get_hexdigit(int i) { return std::string("0123456789ABCDEF").at(i); }
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void write_asc(const Context *ctx, std::ostream &out)
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{
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// [y][x][row][col]
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const ChipInfoPOD &ci = *ctx->chip_info;
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const BitstreamInfoPOD &bi = *ci.bits_info;
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std::vector<std::vector<std::vector<std::vector<int8_t>>>> config;
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config.resize(ci.height);
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for (int y = 0; y < ci.height; y++) {
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config.at(y).resize(ci.width);
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for (int x = 0; x < ci.width; x++) {
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TileType tile = tile_at(ctx, x, y);
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int rows = bi.tiles_nonrouting[tile].rows;
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int cols = bi.tiles_nonrouting[tile].cols;
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config.at(y).at(x).resize(rows, std::vector<int8_t>(cols));
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}
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}
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out << ".comment from next-pnr" << std::endl;
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switch (ctx->args.type) {
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case ArchArgs::LP384:
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out << ".device 384" << std::endl;
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break;
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case ArchArgs::HX1K:
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case ArchArgs::LP1K:
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out << ".device 1k" << std::endl;
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break;
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case ArchArgs::HX8K:
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case ArchArgs::LP8K:
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out << ".device 8k" << std::endl;
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break;
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case ArchArgs::UP5K:
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out << ".device 5k" << std::endl;
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break;
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default:
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assert(false);
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}
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// Set pips
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for (auto pip : ctx->getPips()) {
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if (ctx->pip_to_net[pip.index] != IdString()) {
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const PipInfoPOD &pi = ci.pip_data[pip.index];
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const SwitchInfoPOD &swi = bi.switches[pi.switch_index];
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for (int i = 0; i < swi.num_bits; i++) {
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bool val = (pi.switch_mask & (1 << ((swi.num_bits - 1) - i))) != 0;
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int8_t &cbit = config.at(swi.y).at(swi.x).at(swi.cbits[i].row).at(swi.cbits[i].col);
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if (bool(cbit) != 0)
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assert(false);
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cbit = val;
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}
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}
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}
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// Set logic cell config
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for (auto &cell : ctx->cells) {
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BelId bel = cell.second.get()->bel;
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if (bel == BelId()) {
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std::cout << "Found unplaced cell " << cell.first.str(ctx) << " while generating bitstream!" << std::endl;
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continue;
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}
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const BelInfoPOD &beli = ci.bel_data[bel.index];
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int x = beli.x, y = beli.y, z = beli.z;
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if (cell.second->type == ctx->id("ICESTORM_LC")) {
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const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC];
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unsigned lut_init = get_param_or_def(cell.second.get(), ctx->id("LUT_INIT"));
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bool neg_clk = get_param_or_def(cell.second.get(), ctx->id("NEG_CLK"));
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bool dff_enable = get_param_or_def(cell.second.get(), ctx->id("DFF_ENABLE"));
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bool async_sr = get_param_or_def(cell.second.get(), ctx->id("ASYNC_SR"));
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bool set_noreset = get_param_or_def(cell.second.get(), ctx->id("SET_NORESET"));
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bool carry_enable = get_param_or_def(cell.second.get(), ctx->id("CARRY_ENABLE"));
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std::vector<bool> lc(20, false);
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// From arachne-pnr
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static std::vector<int> lut_perm = {
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4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0,
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};
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for (int i = 0; i < 16; i++) {
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if ((lut_init >> i) & 0x1)
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lc.at(lut_perm.at(i)) = true;
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}
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lc.at(8) = carry_enable;
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lc.at(9) = dff_enable;
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lc.at(18) = set_noreset;
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lc.at(19) = async_sr;
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for (int i = 0; i < 20; i++)
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set_config(ti, config.at(y).at(x), "LC_" + std::to_string(z), lc.at(i), i);
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if (dff_enable)
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set_config(ti, config.at(y).at(x), "NegClk", neg_clk);
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bool carry_const = get_param_or_def(cell.second.get(), ctx->id("CIN_CONST"));
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bool carry_set = get_param_or_def(cell.second.get(), ctx->id("CIN_SET"));
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if (carry_const) {
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if (!ctx->force)
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assert(z == 0);
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set_config(ti, config.at(y).at(x), "CarryInSet", carry_set);
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}
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} else if (cell.second->type == ctx->id("SB_IO")) {
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const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
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unsigned pin_type = get_param_or_def(cell.second.get(), ctx->id("PIN_TYPE"));
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bool neg_trigger = get_param_or_def(cell.second.get(), ctx->id("NEG_TRIGGER"));
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bool pullup = get_param_or_def(cell.second.get(), ctx->id("PULLUP"));
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for (int i = 0; i < 6; i++) {
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bool val = (pin_type >> i) & 0x01;
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set_config(ti, config.at(y).at(x), "IOB_" + std::to_string(z) + ".PINTYPE_" + std::to_string(i), val);
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}
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auto ieren = get_ieren(bi, x, y, z);
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int iex, iey, iez;
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std::tie(iex, iey, iez) = ieren;
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assert(iez != -1);
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bool input_en = false;
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if ((ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_0).index] != IdString()) ||
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(ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_1).index] != IdString())) {
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input_en = true;
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}
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if (ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K) {
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set_config(ti, config.at(iey).at(iex), "IoCtrl.IE_" + std::to_string(iez), !input_en);
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set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), !pullup);
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} else {
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set_config(ti, config.at(iey).at(iex), "IoCtrl.IE_" + std::to_string(iez), input_en);
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set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), !pullup);
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}
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if (ctx->args.type == ArchArgs::UP5K) {
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if (iez == 0) {
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set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_39", !pullup);
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} else if (iez == 1) {
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set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_35", !pullup);
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}
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}
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} else if (cell.second->type == ctx->id("SB_GB")) {
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// no cell config bits
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} else if (cell.second->type == ctx->id("ICESTORM_RAM")) {
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const BelInfoPOD &beli = ci.bel_data[bel.index];
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int x = beli.x, y = beli.y;
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const TileInfoPOD &ti_ramt = bi.tiles_nonrouting[TILE_RAMT];
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const TileInfoPOD &ti_ramb = bi.tiles_nonrouting[TILE_RAMB];
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if (!(ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K)) {
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set_config(ti_ramb, config.at(y).at(x), "RamConfig.PowerUp", true);
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}
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bool negclk_r = get_param_or_def(cell.second.get(), ctx->id("NEG_CLK_R"));
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bool negclk_w = get_param_or_def(cell.second.get(), ctx->id("NEG_CLK_W"));
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int write_mode = get_param_or_def(cell.second.get(), ctx->id("WRITE_MODE"));
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int read_mode = get_param_or_def(cell.second.get(), ctx->id("READ_MODE"));
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set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w);
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set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r);
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set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_0", write_mode & 0x1);
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set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1", write_mode & 0x2);
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set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_2", read_mode & 0x1);
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set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_3", read_mode & 0x2);
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} else if (cell.second->type == ctx->id("SB_WARMBOOT") || cell.second->type == ctx->id("ICESTORM_LFOSC")) {
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// No config needed
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} else if (cell.second->type == ctx->id("ICESTORM_SPRAM")) {
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const BelInfoPOD &beli = ci.bel_data[bel.index];
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int x = beli.x, y = beli.y, z = beli.z;
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assert(ctx->args.type == ArchArgs::UP5K);
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if (x == 0 && y == 0) {
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const TileInfoPOD &ti_ipcon = bi.tiles_nonrouting[TILE_IPCON];
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if (z == 1) {
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set_config(ti_ipcon, config.at(1).at(0), "IpConfig.CBIT_0", true);
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} else if (z == 2) {
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set_config(ti_ipcon, config.at(1).at(0), "IpConfig.CBIT_1", true);
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} else {
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assert(false);
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}
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} else if (x == 25 && y == 0) {
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const TileInfoPOD &ti_ipcon = bi.tiles_nonrouting[TILE_IPCON];
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if (z == 3) {
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set_config(ti_ipcon, config.at(1).at(25), "IpConfig.CBIT_0", true);
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} else if (z == 4) {
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set_config(ti_ipcon, config.at(1).at(25), "IpConfig.CBIT_1", true);
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} else {
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assert(false);
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}
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}
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} else {
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assert(false);
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}
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}
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// Set config bits in unused IO and RAM
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for (auto bel : ctx->getBels()) {
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if (ctx->bel_to_cell[bel.index] == IdString() && ctx->getBelType(bel) == TYPE_SB_IO) {
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const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
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const BelInfoPOD &beli = ci.bel_data[bel.index];
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int x = beli.x, y = beli.y, z = beli.z;
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auto ieren = get_ieren(bi, x, y, z);
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int iex, iey, iez;
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std::tie(iex, iey, iez) = ieren;
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if (iez != -1) {
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if (ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K) {
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set_config(ti, config.at(iey).at(iex), "IoCtrl.IE_" + std::to_string(iez), true);
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set_config(ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), false);
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}
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}
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} else if (ctx->bel_to_cell[bel.index] == IdString() && ctx->getBelType(bel) == TYPE_ICESTORM_RAM) {
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const BelInfoPOD &beli = ci.bel_data[bel.index];
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int x = beli.x, y = beli.y;
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const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_RAMB];
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if ((ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K)) {
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set_config(ti, config.at(y).at(x), "RamConfig.PowerUp", true);
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}
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}
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}
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// Set other config bits
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for (int y = 0; y < ci.height; y++) {
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for (int x = 0; x < ci.width; x++) {
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TileType tile = tile_at(ctx, x, y);
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const TileInfoPOD &ti = bi.tiles_nonrouting[tile];
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// set all ColBufCtrl bits (FIXME)
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bool setColBufCtrl = true;
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if (ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K) {
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if (tile == TILE_RAMB || tile == TILE_RAMT) {
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setColBufCtrl = (y == 3 || y == 5 || y == 11 || y == 13);
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} else {
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setColBufCtrl = (y == 4 || y == 5 || y == 12 || y == 13);
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}
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} else if (ctx->args.type == ArchArgs::LP8K || ctx->args.type == ArchArgs::HX8K) {
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setColBufCtrl = (y == 8 || y == 9 || y == 24 || y == 25);
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} else if (ctx->args.type == ArchArgs::UP5K) {
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setColBufCtrl = (y == 4 || y == 5 || y == 14 || y == 15 || y == 26 || y == 27);
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}
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if (setColBufCtrl) {
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set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_0", true);
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set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_1", true);
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set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_2", true);
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set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_3", true);
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set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_4", true);
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set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_5", true);
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set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_6", true);
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set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_7", true);
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}
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// Weird UltraPlus bits
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if (tile == TILE_DSP0 || tile == TILE_DSP1 || tile == TILE_DSP2 || tile == TILE_DSP3 ||
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tile == TILE_IPCON) {
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if (ctx->args.type == ArchArgs::UP5K && x == 25 && y == 14) {
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// Mystery bits not set in this one tile
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} else {
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for (int lc_idx = 0; lc_idx < 8; lc_idx++) {
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static const std::vector<int> ip_dsp_lut_perm = {
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4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0,
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};
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for (int i = 0; i < 16; i++)
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set_config(ti, config.at(y).at(x), "LC_" + std::to_string(lc_idx), ((i % 8) >= 4),
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ip_dsp_lut_perm.at(i));
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if (tile == TILE_IPCON)
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set_config(ti, config.at(y).at(x),
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"Cascade.IPCON_LC0" + std::to_string(lc_idx) + "_inmux02_5", true);
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else
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set_config(ti, config.at(y).at(x),
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"Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) + "_LC0" +
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std::to_string(lc_idx) + "_inmux02_5",
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true);
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}
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}
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}
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}
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}
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// Write config out
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for (int y = 0; y < ci.height; y++) {
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for (int x = 0; x < ci.width; x++) {
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TileType tile = tile_at(ctx, x, y);
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if (tile == TILE_NONE)
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continue;
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switch (tile) {
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case TILE_LOGIC:
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out << ".logic_tile";
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break;
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case TILE_IO:
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out << ".io_tile";
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break;
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case TILE_RAMB:
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out << ".ramb_tile";
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break;
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case TILE_RAMT:
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out << ".ramt_tile";
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break;
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case TILE_DSP0:
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out << ".dsp0_tile";
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break;
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case TILE_DSP1:
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out << ".dsp1_tile";
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break;
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case TILE_DSP2:
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out << ".dsp2_tile";
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break;
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case TILE_DSP3:
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out << ".dsp3_tile";
|
|
break;
|
|
case TILE_IPCON:
|
|
out << ".ipcon_tile";
|
|
break;
|
|
default:
|
|
assert(false);
|
|
}
|
|
out << " " << x << " " << y << std::endl;
|
|
for (auto row : config.at(y).at(x)) {
|
|
for (auto col : row) {
|
|
if (col == 1)
|
|
out << "1";
|
|
else
|
|
out << "0";
|
|
}
|
|
out << std::endl;
|
|
}
|
|
out << std::endl;
|
|
}
|
|
}
|
|
|
|
// Write RAM init data
|
|
for (auto &cell : ctx->cells) {
|
|
if (cell.second->bel != BelId()) {
|
|
if (cell.second->type == ctx->id("ICESTORM_RAM")) {
|
|
const BelInfoPOD &beli = ci.bel_data[cell.second->bel.index];
|
|
int x = beli.x, y = beli.y;
|
|
out << ".ram_data " << x << " " << y << std::endl;
|
|
for (int w = 0; w < 16; w++) {
|
|
std::vector<bool> bits(256);
|
|
std::string init =
|
|
get_param_str_or_def(cell.second.get(), ctx->id(std::string("INIT_") + get_hexdigit(w)));
|
|
assert(init != "");
|
|
for (size_t i = 0; i < init.size(); i++) {
|
|
bool val = (init.at((init.size() - 1) - i) == '1');
|
|
bits.at(i) = val;
|
|
}
|
|
for (int i = bits.size() - 4; i >= 0; i -= 4) {
|
|
int c = bits.at(i) + (bits.at(i + 1) << 1) + (bits.at(i + 2) << 2) + (bits.at(i + 3) << 3);
|
|
out << char(std::tolower(get_hexdigit(c)));
|
|
}
|
|
out << std::endl;
|
|
}
|
|
out << std::endl;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Write symbols
|
|
// const bool write_symbols = 1;
|
|
for (auto wire : ctx->getWires()) {
|
|
IdString net = ctx->getBoundWireNet(wire);
|
|
if (net != IdString())
|
|
out << ".sym " << wire.index << " " << net.str(ctx) << std::endl;
|
|
}
|
|
}
|
|
|
|
NEXTPNR_NAMESPACE_END
|