77ffdd7fd4
Also move all tests in a tests directory Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
16 lines
239 B
Verilog
16 lines
239 B
Verilog
module top(input clk, input rst, output [7:4] io_led);
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reg [31:0] counter = 32'b0;
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assign io_led = counter >> 22;
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always @(posedge clk)
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begin
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if(rst)
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counter <= 32'b0;
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else
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counter <= counter + 1;
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end
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endmodule
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