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325985e055
nextpnr/himbaechel/uarch/gowin
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YRabbit 325985e055 gowin: Himbaechel. SPX9 BSRAM BUGFIX. 
This type setting is not needed here - the packer distinguishes memory
features by the X9 attribute, which will be correct anyway.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-01-27 15:05:58 +01:00
..
CMakeLists.txt gowin: Himbaechel. Add GW1NZ-1 BSRAM. 2023-11-26 13:08:09 +01:00
constids.inc gowin: Himbaechel. Deal with SP BSRAM ports. 2024-01-23 14:00:29 +01:00
cst.cc gowin: Himbaechel. Extend clock router 2023-09-08 09:15:35 +02:00
cst.h gowin: Himbaechel. Add constraint file processing. 2023-08-31 08:28:09 +02:00
globals.cc gowin: Himbaechel. Fix the style. 2024-01-23 14:00:29 +01:00
globals.h gowin: Himbaechel. Add a clock router. 2023-08-31 08:28:09 +02:00
gowin_arch_gen.py gowin: Himbaechel. Add BSRAM for all chips. 2023-11-26 13:08:09 +01:00
gowin_utils.cc gowin: Himbaechel. Add BSRAM for all chips. 2023-11-26 13:08:09 +01:00
gowin_utils.h gowin: Himbaechel. Deal with SP BSRAM ports. 2024-01-23 14:00:29 +01:00
gowin.cc gowin: Himbaechel. Deal with SP BSRAM ports. 2024-01-23 14:00:29 +01:00
gowin.h gowin: Himbaechel. Add BSRAM for all chips. 2023-11-26 13:08:09 +01:00
pack.cc gowin: Himbaechel. SPX9 BSRAM BUGFIX. 2024-01-27 15:05:58 +01:00
pack.h gowin: Himbaechel. Add ALU. 2023-08-31 08:28:09 +02:00