320 lines
15 KiB
C++
320 lines
15 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 David Shah <david@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "bitstream.h"
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// From Project Trellis
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#include "BitDatabase.hpp"
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#include "Bitstream.hpp"
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#include "Chip.hpp"
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#include "ChipConfig.hpp"
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#include "Tile.hpp"
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#include "TileConfig.hpp"
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#include <fstream>
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#include <streambuf>
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#include "io.h"
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#include "log.h"
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#include "util.h"
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#define fmt_str(x) (static_cast<const std::ostringstream &>(std::ostringstream() << x).str())
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NEXTPNR_NAMESPACE_BEGIN
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// Convert an absolute wire name to a relative Trellis one
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static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
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{
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std::string basename = ctx->locInfo(wire)->wire_data[wire.index].name.get();
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std::string prefix2 = basename.substr(0, 2);
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if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_")
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return basename;
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if (loc == wire.location)
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return basename;
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std::string rel_prefix;
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if (wire.location.y < loc.y)
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rel_prefix += "N" + to_string(loc.y - wire.location.y);
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if (wire.location.y > loc.y)
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rel_prefix += "S" + to_string(wire.location.y - loc.y);
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if (wire.location.x > loc.x)
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rel_prefix += "E" + to_string(wire.location.x - loc.x);
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if (wire.location.x < loc.x)
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rel_prefix += "W" + to_string(loc.x - wire.location.x);
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return rel_prefix + "_" + basename;
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}
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static std::vector<bool> int_to_bitvector(int val, int size)
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{
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std::vector<bool> bv;
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for (int i = 0; i < size; i++) {
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bv.push_back((val & (1 << i)) != 0);
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}
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return bv;
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}
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// Get the PIO tile corresponding to a PIO bel
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static std::string get_pio_tile(Context *ctx, Trellis::Chip &chip, BelId bel)
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{
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static const std::set<std::string> pioabcd_l = {"PICL1", "PICL1_DQS0", "PICL1_DQS3"};
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static const std::set<std::string> pioabcd_r = {"PICR1", "PICR1_DQS0", "PICR1_DQS3"};
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static const std::set<std::string> pioa_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0"};
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static const std::set<std::string> piob_b = {"PICB1", "EFB1_PICB1", "EFB3_PICB1"};
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std::string pio_name = ctx->locInfo(bel)->bel_data[bel.index].name.get();
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if (bel.location.y == 0) {
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if (pio_name == "PIOA") {
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return chip.get_tile_by_position_and_type(0, bel.location.x, "PIOT0");
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} else if (pio_name == "PIOB") {
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return chip.get_tile_by_position_and_type(0, bel.location.x + 1, "PIOT1");
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} else {
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NPNR_ASSERT_FALSE("bad PIO location");
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}
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} else if (bel.location.y == ctx->chip_info->height - 1) {
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if (pio_name == "PIOA") {
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return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, pioa_b);
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} else if (pio_name == "PIOB") {
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return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x + 1, piob_b);
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} else {
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NPNR_ASSERT_FALSE("bad PIO location");
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}
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} else if (bel.location.x == 0) {
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return chip.get_tile_by_position_and_type(bel.location.y + 1, bel.location.x, pioabcd_l);
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} else if (bel.location.x == ctx->chip_info->width - 1) {
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return chip.get_tile_by_position_and_type(bel.location.y + 1, bel.location.x, pioabcd_r);
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} else {
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NPNR_ASSERT_FALSE("bad PIO location");
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}
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}
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// Get the PIC tile corresponding to a PIO bel
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static std::string get_pic_tile(Context *ctx, Trellis::Chip &chip, BelId bel)
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{
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static const std::set<std::string> picab_l = {"PICL0", "PICL0_DQS2"};
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static const std::set<std::string> piccd_l = {"PICL2", "PICL2_DQS1", "MIB_CIB_LR"};
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static const std::set<std::string> picab_r = {"PICR0", "PICR0_DQS2"};
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static const std::set<std::string> piccd_r = {"PICR2", "PICR2_DQS1", "MIB_CIB_LR_A"};
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static const std::set<std::string> pica_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0"};
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static const std::set<std::string> picb_b = {"PICB1", "EFB1_PICB1", "EFB3_PICB1"};
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std::string pio_name = ctx->locInfo(bel)->bel_data[bel.index].name.get();
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if (bel.location.y == 0) {
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if (pio_name == "PIOA") {
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return chip.get_tile_by_position_and_type(1, bel.location.x, "PICT0");
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} else if (pio_name == "PIOB") {
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return chip.get_tile_by_position_and_type(1, bel.location.x + 1, "PICT1");
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} else {
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NPNR_ASSERT_FALSE("bad PIO location");
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}
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} else if (bel.location.y == ctx->chip_info->height - 1) {
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if (pio_name == "PIOA") {
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return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, pica_b);
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} else if (pio_name == "PIOB") {
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return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x + 1, picb_b);
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} else {
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NPNR_ASSERT_FALSE("bad PIO location");
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}
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} else if (bel.location.x == 0) {
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if (pio_name == "PIOA" || pio_name == "PIOB") {
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return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, picab_l);
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} else if (pio_name == "PIOC" || pio_name == "PIOD") {
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return chip.get_tile_by_position_and_type(bel.location.y + 2, bel.location.x, piccd_l);
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} else {
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NPNR_ASSERT_FALSE("bad PIO location");
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}
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} else if (bel.location.x == ctx->chip_info->width - 1) {
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if (pio_name == "PIOA" || pio_name == "PIOB") {
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return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, picab_r);
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} else if (pio_name == "PIOC" || pio_name == "PIOD") {
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return chip.get_tile_by_position_and_type(bel.location.y + 2, bel.location.x, piccd_r);
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} else {
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NPNR_ASSERT_FALSE("bad PIO location");
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}
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} else {
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NPNR_ASSERT_FALSE("bad PIO location");
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}
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}
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void write_bitstream(Context *ctx, std::string base_config_file, std::string text_config_file,
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std::string bitstream_file)
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{
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Trellis::Chip empty_chip(ctx->getChipName());
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Trellis::ChipConfig cc;
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std::set<std::string> cib_tiles = {"CIB", "CIB_LR", "CIB_LR_S", "CIB_EFB0", "CIB_EFB1"};
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if (!base_config_file.empty()) {
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std::ifstream config_file(base_config_file);
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if (!config_file) {
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log_error("failed to open base config file '%s'\n", base_config_file.c_str());
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}
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std::string str((std::istreambuf_iterator<char>(config_file)), std::istreambuf_iterator<char>());
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cc = Trellis::ChipConfig::from_string(str);
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} else {
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cc.chip_name = ctx->getChipName();
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// TODO: .bit metadata
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}
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// Add all set, configurable pips to the config
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for (auto pip : ctx->getPips()) {
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if (ctx->getBoundPipNet(pip) != IdString()) {
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if (ctx->getPipType(pip) == 0) { // ignore fixed pips
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std::string tile = empty_chip.get_tile_by_position_and_type(pip.location.y, pip.location.x,
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ctx->getPipTiletype(pip));
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std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
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std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip));
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cc.tiles[tile].add_arc(sink, source);
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}
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}
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}
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// Find bank voltages
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std::unordered_map<int, IOVoltage> bankVcc;
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std::unordered_map<int, bool> bankLvds;
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (ci->bel != BelId() && ci->type == ctx->id("TRELLIS_IO")) {
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int bank = ctx->getPioBelBank(ci->bel);
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std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT");
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std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
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if (dir != "INPUT") {
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IOVoltage vcc = get_vccio(ioType_from_str(iotype));
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if (bankVcc.find(bank) != bankVcc.end()) {
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// TODO: strong and weak constraints
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if (bankVcc[bank] != vcc) {
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log_error("Error processing '%s': incompatible IO voltages %s and %s on bank %d.",
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cell.first.c_str(ctx), iovoltage_to_str(bankVcc[bank]).c_str(),
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iovoltage_to_str(vcc).c_str(), bank);
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}
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} else {
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bankVcc[bank] = vcc;
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}
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}
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if (iotype == "LVDS")
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bankLvds[bank] = true;
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}
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}
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// Set all bankref tiles to appropriate VccIO
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for (const auto &tile : empty_chip.tiles) {
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std::string type = tile.second->info.type;
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if (type.find("BANKREF") != std::string::npos && type != "BANKREF8") {
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int bank = std::stoi(type.substr(7));
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if (bankVcc.find(bank) != bankVcc.end())
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cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank]));
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if (bankLvds[bank]) {
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cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
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cc.tiles[tile.first].add_enum("BANK.LVDSO", "ON");
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}
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}
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}
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// Configure slices
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (ci->bel == BelId()) {
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log_warning("found unplaced cell '%s' during bitstream gen\n", ci->name.c_str(ctx));
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}
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BelId bel = ci->bel;
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if (ci->type == ctx->id("TRELLIS_SLICE")) {
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std::string tname = empty_chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, "PLC2");
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std::string slice = ctx->locInfo(bel)->bel_data[bel.index].name.get();
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int lut0_init = int_or_default(ci->params, ctx->id("LUT0_INITVAL"));
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int lut1_init = int_or_default(ci->params, ctx->id("LUT1_INITVAL"));
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cc.tiles[tname].add_word(slice + ".K0.INIT", int_to_bitvector(lut0_init, 16));
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cc.tiles[tname].add_word(slice + ".K1.INIT", int_to_bitvector(lut1_init, 16));
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cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, ctx->id("MODE"), "LOGIC"));
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cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
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cc.tiles[tname].add_enum(slice + ".REG0.SD", str_or_default(ci->params, ctx->id("REG0_SD"), "0"));
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cc.tiles[tname].add_enum(slice + ".REG1.SD", str_or_default(ci->params, ctx->id("REG1_SD"), "0"));
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cc.tiles[tname].add_enum(slice + ".REG0.REGSET",
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str_or_default(ci->params, ctx->id("REG0_REGSET"), "RESET"));
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cc.tiles[tname].add_enum(slice + ".REG1.REGSET",
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str_or_default(ci->params, ctx->id("REG1_REGSET"), "RESET"));
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cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, ctx->id("CEMUX"), "1"));
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IdString lsrnet;
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if (ci->ports.find(ctx->id("LSR")) != ci->ports.end() && ci->ports.at(ctx->id("LSR")).net != nullptr)
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lsrnet = ci->ports.at(ctx->id("LSR")).net->name;
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if (ctx->getBoundWireNet(ctx->getWireByName(
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ctx->id(fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/LSR0")))) == lsrnet) {
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cc.tiles[tname].add_enum("LSR0.SRMODE", str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
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cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, ctx->id("LSRMUX"), "LSR"));
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} else if (ctx->getBoundWireNet(ctx->getWireByName(ctx->id(
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fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/LSR1")))) == lsrnet) {
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cc.tiles[tname].add_enum("LSR1.SRMODE", str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
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cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, ctx->id("LSRMUX"), "LSR"));
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}
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// TODO: CLKMUX, CEMUX, carry
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} else if (ci->type == ctx->id("TRELLIS_IO")) {
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std::string pio = ctx->locInfo(bel)->bel_data[bel.index].name.get();
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std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
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std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT");
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std::string pio_tile = get_pio_tile(ctx, empty_chip, bel);
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std::string pic_tile = get_pic_tile(ctx, empty_chip, bel);
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cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
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cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
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if (is_differential(ioType_from_str(iotype))) {
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// Explicitly disable other pair
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std::string other;
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if (pio == "PIOA")
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other = "PIOB";
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else if (pio == "PIOC")
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other = "PIOD";
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else
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log_error("cannot place differential IO at location %s\n", pio.c_str());
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//cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
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//cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
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cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE");
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cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
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}
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if (dir != "INPUT" &&
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(ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) {
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// Tie tristate low if unconnected for outputs or bidir
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std::string jpt = fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/JPADDT" << pio.back());
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WireId jpt_wire = ctx->getWireByName(ctx->id(jpt));
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PipId jpt_pip = *ctx->getPipsUphill(jpt_wire).begin();
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WireId cib_wire = ctx->getPipSrcWire(jpt_pip);
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std::string cib_tile =
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empty_chip.get_tile_by_position_and_type(cib_wire.location.y, cib_wire.location.x, cib_tiles);
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std::string cib_wirename = ctx->locInfo(cib_wire)->wire_data[cib_wire.index].name.get();
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cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0");
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}
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if (dir == "INPUT" && !is_differential(ioType_from_str(iotype))) {
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cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", "ON");
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}
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} else {
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NPNR_ASSERT_FALSE("unsupported cell type");
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}
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}
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// Configure chip
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Trellis::Chip cfg_chip = cc.to_chip();
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if (!bitstream_file.empty()) {
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Trellis::Bitstream::serialise_chip(cfg_chip).write_bit_py(bitstream_file);
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}
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if (!text_config_file.empty()) {
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std::ofstream out_config(text_config_file);
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out_config << cc.to_string();
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}
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}
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NEXTPNR_NAMESPACE_END
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