23 lines
451 B
Verilog
23 lines
451 B
Verilog
module blinky_tb;
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reg clk;
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always #5 clk = (clk === 1'b0);
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wire led1, led2, led3, led4, led5;
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chip uut (
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.io_0_8_1(clk),
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.io_13_12_1(led1),
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.io_13_12_0(led2),
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.io_13_11_1(led3),
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.io_13_11_0(led4),
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.io_13_9_1(led5)
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);
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initial begin
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$dumpfile("blinky_tb.vcd");
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$dumpvars(0, blinky_tb);
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repeat (9000000) @(posedge clk);
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$finish;
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end
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endmodule
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