910 lines
27 KiB
C++
910 lines
27 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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* Copyright (C) 2018 Serge Bazanski <q3k@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <algorithm>
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#include <cmath>
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#include "cells.h"
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#include "gfx.h"
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#include "log.h"
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#include "nextpnr.h"
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#include "placer1.h"
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#include "router1.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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// -----------------------------------------------------------------------
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IdString Arch::belTypeToId(BelType type) const
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{
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if (type == TYPE_ICESTORM_LC)
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return id("ICESTORM_LC");
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if (type == TYPE_ICESTORM_RAM)
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return id("ICESTORM_RAM");
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if (type == TYPE_SB_IO)
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return id("SB_IO");
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if (type == TYPE_SB_GB)
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return id("SB_GB");
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if (type == TYPE_ICESTORM_PLL)
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return id("ICESTORM_PLL");
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if (type == TYPE_SB_WARMBOOT)
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return id("SB_WARMBOOT");
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if (type == TYPE_ICESTORM_DSP)
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return id("ICESTORM_DSP");
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if (type == TYPE_ICESTORM_HFOSC)
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return id("ICESTORM_HFOSC");
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if (type == TYPE_ICESTORM_LFOSC)
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return id("ICESTORM_LFOSC");
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if (type == TYPE_SB_I2C)
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return id("SB_I2C");
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if (type == TYPE_SB_SPI)
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return id("SB_SPI");
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if (type == TYPE_IO_I3C)
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return id("IO_I3C");
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if (type == TYPE_SB_LEDDA_IP)
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return id("SB_LEDDA_IP");
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if (type == TYPE_SB_RGBA_DRV)
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return id("SB_RGBA_DRV");
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if (type == TYPE_ICESTORM_SPRAM)
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return id("ICESTORM_SPRAM");
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return IdString();
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}
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BelType Arch::belTypeFromId(IdString type) const
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{
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if (type == id("ICESTORM_LC"))
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return TYPE_ICESTORM_LC;
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if (type == id("ICESTORM_RAM"))
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return TYPE_ICESTORM_RAM;
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if (type == id("SB_IO"))
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return TYPE_SB_IO;
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if (type == id("SB_GB"))
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return TYPE_SB_GB;
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if (type == id("ICESTORM_PLL"))
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return TYPE_ICESTORM_PLL;
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if (type == id("SB_WARMBOOT"))
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return TYPE_SB_WARMBOOT;
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if (type == id("ICESTORM_DSP"))
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return TYPE_ICESTORM_DSP;
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if (type == id("ICESTORM_HFOSC"))
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return TYPE_ICESTORM_HFOSC;
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if (type == id("ICESTORM_LFOSC"))
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return TYPE_ICESTORM_LFOSC;
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if (type == id("SB_I2C"))
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return TYPE_SB_I2C;
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if (type == id("SB_SPI"))
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return TYPE_SB_SPI;
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if (type == id("IO_I3C"))
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return TYPE_IO_I3C;
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if (type == id("SB_LEDDA_IP"))
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return TYPE_SB_LEDDA_IP;
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if (type == id("SB_RGBA_DRV"))
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return TYPE_SB_RGBA_DRV;
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if (type == id("ICESTORM_SPRAM"))
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return TYPE_ICESTORM_SPRAM;
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return TYPE_NONE;
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}
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// -----------------------------------------------------------------------
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void IdString::initialize_arch(const BaseCtx *ctx)
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{
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#define X(t) initialize_add(ctx, #t, PIN_##t);
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#include "portpins.inc"
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#undef X
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}
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IdString Arch::portPinToId(PortPin type) const
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{
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IdString ret;
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if (type > 0 && type < PIN_MAXIDX)
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ret.index = type;
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return ret;
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}
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PortPin Arch::portPinFromId(IdString type) const
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{
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if (type.index > 0 && type.index < PIN_MAXIDX)
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return PortPin(type.index);
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return PIN_NONE;
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}
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// -----------------------------------------------------------------------
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static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
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#if defined(_MSC_VER)
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void load_chipdb();
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#endif
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Arch::Arch(ArchArgs args) : args(args)
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{
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#if defined(_MSC_VER)
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load_chipdb();
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#endif
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#ifdef ICE40_HX1K_ONLY
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if (args.type == ArchArgs::HX1K) {
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fast_part = true;
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chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
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} else {
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log_error("Unsupported iCE40 chip type.\n");
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}
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#else
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if (args.type == ArchArgs::LP384) {
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fast_part = false;
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chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_384));
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} else if (args.type == ArchArgs::LP1K || args.type == ArchArgs::HX1K) {
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fast_part = args.type == ArchArgs::HX1K;
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chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
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} else if (args.type == ArchArgs::UP5K) {
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fast_part = false;
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chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_5k));
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} else if (args.type == ArchArgs::LP8K || args.type == ArchArgs::HX8K) {
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fast_part = args.type == ArchArgs::HX8K;
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chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_8k));
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} else {
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log_error("Unsupported iCE40 chip type.\n");
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}
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#endif
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package_info = nullptr;
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for (int i = 0; i < chip_info->num_packages; i++) {
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if (chip_info->packages_data[i].name.get() == args.package) {
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package_info = &(chip_info->packages_data[i]);
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break;
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}
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}
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if (package_info == nullptr)
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log_error("Unsupported package '%s'.\n", args.package.c_str());
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bel_to_cell.resize(chip_info->num_bels);
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wire_to_net.resize(chip_info->num_wires);
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pip_to_net.resize(chip_info->num_pips);
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switches_locked.resize(chip_info->num_switches);
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// Initialise regularly used IDStrings for performance
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id_glb_buf_out = id("GLOBAL_BUFFER_OUTPUT");
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id_icestorm_lc = id("ICESTORM_LC");
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id_sb_io = id("SB_IO");
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id_sb_gb = id("SB_GB");
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id_cen = id("CEN");
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id_clk = id("CLK");
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id_sr = id("SR");
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id_i0 = id("I0");
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id_i1 = id("I1");
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id_i2 = id("I2");
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id_i3 = id("I3");
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id_dff_en = id("DFF_ENABLE");
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id_neg_clk = id("NEG_CLK");
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id_cin = id("CIN");
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id_cout = id("COUT");
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id_o = id("O");
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id_lo = id("LO");
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id_icestorm_ram = id("ICESTORM_RAM");
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id_rclk = id("RCLK");
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id_wclk = id("WCLK");
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}
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// -----------------------------------------------------------------------
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std::string Arch::getChipName()
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{
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#ifdef ICE40_HX1K_ONLY
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if (args.type == ArchArgs::HX1K) {
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return "Lattice LP1K";
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} else {
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log_error("Unsupported iCE40 chip type.\n");
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}
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#else
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if (args.type == ArchArgs::LP384) {
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return "Lattice LP384";
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} else if (args.type == ArchArgs::LP1K) {
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return "Lattice LP1K";
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} else if (args.type == ArchArgs::HX1K) {
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return "Lattice HX1K";
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} else if (args.type == ArchArgs::UP5K) {
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return "Lattice UP5K";
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} else if (args.type == ArchArgs::LP8K) {
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return "Lattice LP8K";
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} else if (args.type == ArchArgs::HX8K) {
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return "Lattice HX8K";
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} else {
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log_error("Unknown chip\n");
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}
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#endif
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}
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// -----------------------------------------------------------------------
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IdString Arch::archArgsToId(ArchArgs args) const
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{
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if (args.type == ArchArgs::LP384)
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return id("lp384");
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if (args.type == ArchArgs::LP1K)
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return id("lp1k");
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if (args.type == ArchArgs::HX1K)
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return id("hx1k");
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if (args.type == ArchArgs::UP5K)
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return id("up5k");
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if (args.type == ArchArgs::LP8K)
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return id("lp8k");
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if (args.type == ArchArgs::HX8K)
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return id("hx8k");
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return IdString();
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}
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// -----------------------------------------------------------------------
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BelId Arch::getBelByName(IdString name) const
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{
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BelId ret;
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if (bel_by_name.empty()) {
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for (int i = 0; i < chip_info->num_bels; i++)
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bel_by_name[id(chip_info->bel_data[i].name.get())] = i;
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}
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auto it = bel_by_name.find(name);
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if (it != bel_by_name.end())
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ret.index = it->second;
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return ret;
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}
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BelId Arch::getBelByLocation(Loc loc) const
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{
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BelId bel;
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if (bel_by_loc.empty()) {
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for (int i = 0; i < chip_info->num_bels; i++) {
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BelId b;
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b.index = i;
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bel_by_loc[getBelLocation(b)] = i;
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}
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}
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auto it = bel_by_loc.find(loc);
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if (it != bel_by_loc.end())
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bel.index = it->second;
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return bel;
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}
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BelRange Arch::getBelsByTile(int x, int y) const
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{
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// In iCE40 chipdb bels at the same tile are consecutive and dense z ordinates are used
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BelRange br;
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br.b.cursor = Arch::getBelByLocation(Loc(x, y, 0)).index;
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br.e.cursor = br.b.cursor;
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if (br.e.cursor != -1) {
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while (br.e.cursor < chip_info->num_bels && chip_info->bel_data[br.e.cursor].x == x &&
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chip_info->bel_data[br.e.cursor].y == y)
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br.e.cursor++;
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}
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return br;
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}
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PortType Arch::getBelPinType(BelId bel, PortPin pin) const
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{
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NPNR_ASSERT(bel != BelId());
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int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
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const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
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if (num_bel_wires < 7) {
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for (int i = 0; i < num_bel_wires; i++) {
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if (bel_wires[i].port == pin)
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return PortType(bel_wires[i].type);
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}
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} else {
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int b = 0, e = num_bel_wires-1;
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while (b <= e) {
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int i = (b+e) / 2;
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if (bel_wires[i].port == pin)
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return PortType(bel_wires[i].type);
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if (bel_wires[i].port > pin)
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e = i-1;
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else
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b = i+1;
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}
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}
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return PORT_INOUT;
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}
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WireId Arch::getBelPinWire(BelId bel, PortPin pin) const
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{
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WireId ret;
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NPNR_ASSERT(bel != BelId());
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int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
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const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
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if (num_bel_wires < 7) {
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for (int i = 0; i < num_bel_wires; i++) {
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if (bel_wires[i].port == pin) {
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ret.index = bel_wires[i].wire_index;
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break;
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}
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}
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} else {
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int b = 0, e = num_bel_wires-1;
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while (b <= e) {
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int i = (b+e) / 2;
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if (bel_wires[i].port == pin) {
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ret.index = bel_wires[i].wire_index;
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break;
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}
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if (bel_wires[i].port > pin)
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e = i-1;
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else
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b = i+1;
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}
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}
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return ret;
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}
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std::vector<PortPin> Arch::getBelPins(BelId bel) const
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{
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std::vector<PortPin> ret;
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NPNR_ASSERT(bel != BelId());
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int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
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const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
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for (int i = 0; i < num_bel_wires; i++)
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ret.push_back(bel_wires[i].port);
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return ret;
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}
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// -----------------------------------------------------------------------
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WireId Arch::getWireByName(IdString name) const
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{
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WireId ret;
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if (wire_by_name.empty()) {
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for (int i = 0; i < chip_info->num_wires; i++)
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wire_by_name[id(chip_info->wire_data[i].name.get())] = i;
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}
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auto it = wire_by_name.find(name);
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if (it != wire_by_name.end())
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ret.index = it->second;
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return ret;
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}
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// -----------------------------------------------------------------------
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PipId Arch::getPipByName(IdString name) const
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{
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PipId ret;
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if (pip_by_name.empty()) {
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for (int i = 0; i < chip_info->num_pips; i++) {
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PipId pip;
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pip.index = i;
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pip_by_name[getPipName(pip)] = i;
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}
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}
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auto it = pip_by_name.find(name);
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if (it != pip_by_name.end())
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ret.index = it->second;
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return ret;
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}
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IdString Arch::getPipName(PipId pip) const
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{
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NPNR_ASSERT(pip != PipId());
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#if 1
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int x = chip_info->pip_data[pip.index].x;
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int y = chip_info->pip_data[pip.index].y;
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std::string src_name = chip_info->wire_data[chip_info->pip_data[pip.index].src].name.get();
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std::replace(src_name.begin(), src_name.end(), '/', '.');
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std::string dst_name = chip_info->wire_data[chip_info->pip_data[pip.index].dst].name.get();
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std::replace(dst_name.begin(), dst_name.end(), '/', '.');
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return id("X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" + src_name + ".->." + dst_name);
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#else
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return id(chip_info->pip_data[pip.index].name.get());
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#endif
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}
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// -----------------------------------------------------------------------
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BelId Arch::getPackagePinBel(const std::string &pin) const
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{
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for (int i = 0; i < package_info->num_pins; i++) {
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if (package_info->pins[i].name.get() == pin) {
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BelId id;
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id.index = package_info->pins[i].bel_index;
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return id;
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}
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}
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return BelId();
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}
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std::string Arch::getBelPackagePin(BelId bel) const
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{
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for (int i = 0; i < package_info->num_pins; i++) {
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if (package_info->pins[i].bel_index == bel.index) {
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return std::string(package_info->pins[i].name.get());
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}
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}
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return "";
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}
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// -----------------------------------------------------------------------
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GroupId Arch::getGroupByName(IdString name) const
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{
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for (auto g : getGroups())
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if (getGroupName(g) == name)
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return g;
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return GroupId();
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}
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IdString Arch::getGroupName(GroupId group) const
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{
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std::string suffix;
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switch (group.type) {
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case GroupId::TYPE_FRAME:
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suffix = "tile";
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break;
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case GroupId::TYPE_MAIN_SW:
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suffix = "main_sw";
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break;
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case GroupId::TYPE_LOCAL_SW:
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suffix = "local_sw";
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break;
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case GroupId::TYPE_LC0_SW:
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suffix = "lc0_sw";
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break;
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case GroupId::TYPE_LC1_SW:
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suffix = "lc1_sw";
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break;
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case GroupId::TYPE_LC2_SW:
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suffix = "lc2_sw";
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break;
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case GroupId::TYPE_LC3_SW:
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suffix = "lc3_sw";
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break;
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case GroupId::TYPE_LC4_SW:
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suffix = "lc4_sw";
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break;
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case GroupId::TYPE_LC5_SW:
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suffix = "lc5_sw";
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break;
|
|
case GroupId::TYPE_LC6_SW:
|
|
suffix = "lc6_sw";
|
|
break;
|
|
case GroupId::TYPE_LC7_SW:
|
|
suffix = "lc7_sw";
|
|
break;
|
|
default:
|
|
return IdString();
|
|
}
|
|
|
|
return id("X" + std::to_string(group.x) + "/Y" + std::to_string(group.y) + "/" + suffix);
|
|
}
|
|
|
|
std::vector<GroupId> Arch::getGroups() const
|
|
{
|
|
std::vector<GroupId> ret;
|
|
|
|
for (int y = 0; y < chip_info->height; y++) {
|
|
for (int x = 0; x < chip_info->width; x++) {
|
|
TileType type = chip_info->tile_grid[y * chip_info->width + x];
|
|
if (type == TILE_NONE)
|
|
continue;
|
|
|
|
GroupId group;
|
|
group.type = GroupId::TYPE_FRAME;
|
|
group.x = x;
|
|
group.y = y;
|
|
// ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_MAIN_SW;
|
|
ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_LOCAL_SW;
|
|
ret.push_back(group);
|
|
|
|
#if 0
|
|
if (type == TILE_LOGIC)
|
|
{
|
|
group.type = GroupId::TYPE_LC0_SW;
|
|
ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_LC1_SW;
|
|
ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_LC2_SW;
|
|
ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_LC3_SW;
|
|
ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_LC4_SW;
|
|
ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_LC5_SW;
|
|
ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_LC6_SW;
|
|
ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_LC7_SW;
|
|
ret.push_back(group);
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
std::vector<BelId> Arch::getGroupBels(GroupId group) const
|
|
{
|
|
std::vector<BelId> ret;
|
|
return ret;
|
|
}
|
|
|
|
std::vector<WireId> Arch::getGroupWires(GroupId group) const
|
|
{
|
|
std::vector<WireId> ret;
|
|
return ret;
|
|
}
|
|
|
|
std::vector<PipId> Arch::getGroupPips(GroupId group) const
|
|
{
|
|
std::vector<PipId> ret;
|
|
return ret;
|
|
}
|
|
|
|
std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
|
|
{
|
|
std::vector<GroupId> ret;
|
|
return ret;
|
|
}
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
delay_t Arch::estimateDelay(WireId src, WireId dst) const
|
|
{
|
|
NPNR_ASSERT(src != WireId());
|
|
int x1 = chip_info->wire_data[src.index].x;
|
|
int y1 = chip_info->wire_data[src.index].y;
|
|
|
|
NPNR_ASSERT(dst != WireId());
|
|
int x2 = chip_info->wire_data[dst.index].x;
|
|
int y2 = chip_info->wire_data[dst.index].y;
|
|
|
|
int xd = x2 - x1, yd = y2 - y1;
|
|
int xscale = 120, yscale = 120, offset = 0;
|
|
|
|
// if (chip_info->wire_data[src.index].type == WIRE_TYPE_SP4_VERT) {
|
|
// yd = yd < -4 ? yd + 4 : (yd < 0 ? 0 : yd);
|
|
// offset = 500;
|
|
// }
|
|
|
|
return xscale * abs(xd) + yscale * abs(yd) + offset;
|
|
}
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
bool Arch::place() { return placer1(getCtx()); }
|
|
|
|
bool Arch::route() { return router1(getCtx()); }
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
DecalXY Arch::getFrameDecal() const
|
|
{
|
|
DecalXY decalxy;
|
|
decalxy.decal.type = DecalId::TYPE_FRAME;
|
|
decalxy.decal.active = true;
|
|
return decalxy;
|
|
}
|
|
|
|
DecalXY Arch::getBelDecal(BelId bel) const
|
|
{
|
|
DecalXY decalxy;
|
|
decalxy.decal.type = DecalId::TYPE_BEL;
|
|
decalxy.decal.index = bel.index;
|
|
decalxy.decal.active = bel_to_cell.at(bel.index) != IdString();
|
|
return decalxy;
|
|
}
|
|
|
|
DecalXY Arch::getWireDecal(WireId wire) const
|
|
{
|
|
DecalXY decalxy;
|
|
decalxy.decal.type = DecalId::TYPE_WIRE;
|
|
decalxy.decal.index = wire.index;
|
|
decalxy.decal.active = wire_to_net.at(wire.index) != IdString();
|
|
return decalxy;
|
|
}
|
|
|
|
DecalXY Arch::getPipDecal(PipId pip) const
|
|
{
|
|
DecalXY decalxy;
|
|
decalxy.decal.type = DecalId::TYPE_PIP;
|
|
decalxy.decal.index = pip.index;
|
|
decalxy.decal.active = pip_to_net.at(pip.index) != IdString();
|
|
return decalxy;
|
|
};
|
|
|
|
DecalXY Arch::getGroupDecal(GroupId group) const
|
|
{
|
|
DecalXY decalxy;
|
|
decalxy.decal.type = DecalId::TYPE_GROUP;
|
|
decalxy.decal.index = (group.type << 16) | (group.x << 8) | (group.y);
|
|
decalxy.decal.active = true;
|
|
return decalxy;
|
|
};
|
|
|
|
std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
|
|
{
|
|
std::vector<GraphicElement> ret;
|
|
|
|
if (decal.type == DecalId::TYPE_FRAME) {
|
|
/* nothing */
|
|
}
|
|
|
|
if (decal.type == DecalId::TYPE_GROUP) {
|
|
int type = (decal.index >> 16) & 255;
|
|
int x = (decal.index >> 8) & 255;
|
|
int y = decal.index & 255;
|
|
|
|
if (type == GroupId::TYPE_FRAME) {
|
|
GraphicElement el;
|
|
el.type = GraphicElement::TYPE_LINE;
|
|
el.style = GraphicElement::STYLE_FRAME;
|
|
|
|
el.x1 = x + 0.01, el.x2 = x + 0.02, el.y1 = y + 0.01, el.y2 = y + 0.01;
|
|
ret.push_back(el);
|
|
el.x1 = x + 0.01, el.x2 = x + 0.01, el.y1 = y + 0.01, el.y2 = y + 0.02;
|
|
ret.push_back(el);
|
|
|
|
el.x1 = x + 0.99, el.x2 = x + 0.98, el.y1 = y + 0.01, el.y2 = y + 0.01;
|
|
ret.push_back(el);
|
|
el.x1 = x + 0.99, el.x2 = x + 0.99, el.y1 = y + 0.01, el.y2 = y + 0.02;
|
|
ret.push_back(el);
|
|
|
|
el.x1 = x + 0.99, el.x2 = x + 0.98, el.y1 = y + 0.99, el.y2 = y + 0.99;
|
|
ret.push_back(el);
|
|
el.x1 = x + 0.99, el.x2 = x + 0.99, el.y1 = y + 0.99, el.y2 = y + 0.98;
|
|
ret.push_back(el);
|
|
|
|
el.x1 = x + 0.01, el.x2 = x + 0.02, el.y1 = y + 0.99, el.y2 = y + 0.99;
|
|
ret.push_back(el);
|
|
el.x1 = x + 0.01, el.x2 = x + 0.01, el.y1 = y + 0.99, el.y2 = y + 0.98;
|
|
ret.push_back(el);
|
|
}
|
|
|
|
if (type == GroupId::TYPE_MAIN_SW) {
|
|
GraphicElement el;
|
|
el.type = GraphicElement::TYPE_BOX;
|
|
el.style = GraphicElement::STYLE_FRAME;
|
|
|
|
el.x1 = x + main_swbox_x1;
|
|
el.x2 = x + main_swbox_x2;
|
|
el.y1 = y + main_swbox_y1;
|
|
el.y2 = y + main_swbox_y2;
|
|
ret.push_back(el);
|
|
}
|
|
|
|
if (type == GroupId::TYPE_LOCAL_SW) {
|
|
GraphicElement el;
|
|
el.type = GraphicElement::TYPE_BOX;
|
|
el.style = GraphicElement::STYLE_FRAME;
|
|
|
|
el.x1 = x + local_swbox_x1;
|
|
el.x2 = x + local_swbox_x2;
|
|
el.y1 = y + local_swbox_y1;
|
|
el.y2 = y + local_swbox_y2;
|
|
ret.push_back(el);
|
|
}
|
|
}
|
|
|
|
if (decal.type == DecalId::TYPE_WIRE) {
|
|
int n = chip_info->wire_data[decal.index].num_segments;
|
|
const WireSegmentPOD *p = chip_info->wire_data[decal.index].segments.get();
|
|
|
|
GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
|
|
|
|
for (int i = 0; i < n; i++)
|
|
gfxTileWire(ret, p[i].x, p[i].y, GfxTileWireId(p[i].index), style);
|
|
}
|
|
|
|
if (decal.type == DecalId::TYPE_PIP) {
|
|
const PipInfoPOD &p = chip_info->pip_data[decal.index];
|
|
GraphicElement::style_t style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_HIDDEN;
|
|
gfxTilePip(ret, p.x, p.y, GfxTileWireId(p.src_seg), GfxTileWireId(p.dst_seg), style);
|
|
}
|
|
|
|
if (decal.type == DecalId::TYPE_BEL) {
|
|
BelId bel;
|
|
bel.index = decal.index;
|
|
|
|
auto bel_type = getBelType(bel);
|
|
|
|
if (bel_type == TYPE_ICESTORM_LC) {
|
|
GraphicElement el;
|
|
el.type = GraphicElement::TYPE_BOX;
|
|
el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
|
|
el.x1 = chip_info->bel_data[bel.index].x + logic_cell_x1;
|
|
el.x2 = chip_info->bel_data[bel.index].x + logic_cell_x2;
|
|
el.y1 = chip_info->bel_data[bel.index].y + logic_cell_y1 +
|
|
(chip_info->bel_data[bel.index].z) * logic_cell_pitch;
|
|
el.y2 = chip_info->bel_data[bel.index].y + logic_cell_y2 +
|
|
(chip_info->bel_data[bel.index].z) * logic_cell_pitch;
|
|
ret.push_back(el);
|
|
}
|
|
|
|
if (bel_type == TYPE_SB_IO) {
|
|
GraphicElement el;
|
|
el.type = GraphicElement::TYPE_BOX;
|
|
el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
|
|
el.x1 = chip_info->bel_data[bel.index].x + logic_cell_x1;
|
|
el.x2 = chip_info->bel_data[bel.index].x + logic_cell_x2;
|
|
el.y1 = chip_info->bel_data[bel.index].y + logic_cell_y1 +
|
|
(4 * chip_info->bel_data[bel.index].z) * logic_cell_pitch;
|
|
el.y2 = chip_info->bel_data[bel.index].y + logic_cell_y2 +
|
|
(4 * chip_info->bel_data[bel.index].z + 3) * logic_cell_pitch;
|
|
ret.push_back(el);
|
|
}
|
|
|
|
if (bel_type == TYPE_ICESTORM_RAM) {
|
|
for (int i = 0; i < 2; i++) {
|
|
GraphicElement el;
|
|
el.type = GraphicElement::TYPE_BOX;
|
|
el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
|
|
el.x1 = chip_info->bel_data[bel.index].x + logic_cell_x1;
|
|
el.x2 = chip_info->bel_data[bel.index].x + logic_cell_x2;
|
|
el.y1 = chip_info->bel_data[bel.index].y + logic_cell_y1 + i;
|
|
el.y2 = chip_info->bel_data[bel.index].y + logic_cell_y2 + i + 7 * logic_cell_pitch;
|
|
ret.push_back(el);
|
|
}
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
|
|
{
|
|
if (cell->type == id_icestorm_lc) {
|
|
if ((fromPort == id_i0 || fromPort == id_i1 || fromPort == id_i2 || fromPort == id_i3) &&
|
|
(toPort == id_o || toPort == id_lo)) {
|
|
delay.delay = 450;
|
|
return true;
|
|
} else if (fromPort == id_cin && toPort == id_cout) {
|
|
delay.delay = 120;
|
|
return true;
|
|
} else if (fromPort == id_i1 && toPort == id_cout) {
|
|
delay.delay = 260;
|
|
return true;
|
|
} else if (fromPort == id_i2 && toPort == id_cout) {
|
|
delay.delay = 230;
|
|
return true;
|
|
} else if (fromPort == id_clk && toPort == id_o) {
|
|
delay.delay = 540;
|
|
return true;
|
|
}
|
|
} else if (cell->type == id_icestorm_ram) {
|
|
if (fromPort == id_rclk) {
|
|
delay.delay = 2140;
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
IdString Arch::getPortClock(const CellInfo *cell, IdString port) const
|
|
{
|
|
if (cell->type == id_icestorm_lc && cell->lcInfo.dffEnable) {
|
|
if (port != id_lo && port != id_cin && port != id_cout)
|
|
return id_clk;
|
|
} else if (cell->type == id_icestorm_ram) {
|
|
if (port.str(this)[0] == 'R')
|
|
return id_rclk;
|
|
else
|
|
return id_wclk;
|
|
}
|
|
return IdString();
|
|
}
|
|
|
|
bool Arch::isClockPort(const CellInfo *cell, IdString port) const
|
|
{
|
|
if (cell->type == id("ICESTORM_LC") && port == id("CLK"))
|
|
return true;
|
|
if (cell->type == id("ICESTORM_RAM") && (port == id("RCLK") || (port == id("WCLK"))))
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
bool Arch::isGlobalNet(const NetInfo *net) const
|
|
{
|
|
if (net == nullptr)
|
|
return false;
|
|
return net->driver.cell != nullptr && net->driver.port == id_glb_buf_out;
|
|
}
|
|
|
|
// Assign arch arg info
|
|
void Arch::assignArchInfo()
|
|
{
|
|
for (auto &net : getCtx()->nets) {
|
|
NetInfo *ni = net.second.get();
|
|
if (isGlobalNet(ni))
|
|
ni->is_global = true;
|
|
ni->is_enable = false;
|
|
ni->is_reset = false;
|
|
for (auto usr : ni->users) {
|
|
if (is_enable_port(this, usr))
|
|
ni->is_enable = true;
|
|
if (is_reset_port(this, usr))
|
|
ni->is_reset = true;
|
|
}
|
|
}
|
|
for (auto &cell : getCtx()->cells) {
|
|
CellInfo *ci = cell.second.get();
|
|
assignCellInfo(ci);
|
|
}
|
|
}
|
|
|
|
void Arch::assignCellInfo(CellInfo *cell)
|
|
{
|
|
cell->belType = belTypeFromId(cell->type);
|
|
if (cell->type == id_icestorm_lc) {
|
|
cell->lcInfo.dffEnable = bool_or_default(cell->params, id_dff_en);
|
|
cell->lcInfo.negClk = bool_or_default(cell->params, id_neg_clk);
|
|
cell->lcInfo.clk = get_net_or_empty(cell, id_clk);
|
|
cell->lcInfo.cen = get_net_or_empty(cell, id_cen);
|
|
cell->lcInfo.sr = get_net_or_empty(cell, id_sr);
|
|
cell->lcInfo.inputCount = 0;
|
|
if (get_net_or_empty(cell, id_i0))
|
|
cell->lcInfo.inputCount++;
|
|
if (get_net_or_empty(cell, id_i1))
|
|
cell->lcInfo.inputCount++;
|
|
if (get_net_or_empty(cell, id_i2))
|
|
cell->lcInfo.inputCount++;
|
|
if (get_net_or_empty(cell, id_i3))
|
|
cell->lcInfo.inputCount++;
|
|
}
|
|
}
|
|
|
|
NEXTPNR_NAMESPACE_END
|