129 lines
3.6 KiB
C++
129 lines
3.6 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021 Symbiflow Authors
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef LUTS_H
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#define LUTS_H
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#include "idstring.h"
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#include "nextpnr_namespaces.h"
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#include "dynamic_bitarray.h"
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#include "hashlib.h"
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NEXTPNR_NAMESPACE_BEGIN
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struct CellInfo;
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struct Context;
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struct SiteLutMappingResult;
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enum LogicLevel
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{
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LL_Zero,
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LL_One,
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LL_DontCare
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};
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struct LutCell
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{
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// LUT cell pins for equation, LSB first.
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std::vector<IdString> pins;
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pool<IdString> lut_pins;
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pool<IdString> vcc_pins;
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DynamicBitarray<> equation;
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};
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struct LutBel
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{
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IdString name;
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// LUT BEL pins to LUT array index.
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std::vector<IdString> pins;
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dict<IdString, size_t> pin_to_index;
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IdString output_pin;
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// What part of the LUT equation does this LUT output use?
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// This assumes contiguous LUT bits.
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uint32_t low_bit;
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uint32_t high_bit;
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int32_t min_pin;
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int32_t max_pin;
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};
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struct SiteLutMapping
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{
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struct LutCellMapping
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{
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LutCell lut_cell;
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};
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};
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// Work forward from cell definition and cell -> bel pin map and check that
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// equation is valid.
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void check_equation(const LutCell &lut_cell, const dict<IdString, IdString> &cell_to_bel_map, const LutBel &lut_bel,
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const std::vector<LogicLevel> &equation, uint32_t used_pins);
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struct LutElement
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{
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size_t width;
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dict<IdString, LutBel> lut_bels;
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void compute_pin_order();
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std::vector<IdString> pins;
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dict<IdString, size_t> pin_to_index;
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};
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struct LutMapper
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{
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LutMapper(const LutElement &element) : element(element) {}
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const LutElement &element;
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std::vector<CellInfo *> cells;
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bool remap_luts(const Context *ctx, SiteLutMappingResult *lut_mapping,
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pool<const LutBel *, hash_ptr_ops> *blocked_luts);
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// Determine which wires given the current mapping must be tied to the
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// default constant.
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//
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// Returns a bit mask, 1 meaning it must be tied. Otherwise means that
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// the pin is free to be a signal.
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uint32_t check_wires(const std::vector<std::vector<int32_t>> &bel_to_cell_pin_remaps,
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const std::vector<const LutBel *> &lut_bels, uint32_t used_pins,
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pool<const LutBel *, hash_ptr_ops> *blocked_luts) const;
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// Version of check_wires that uses current state of cells based on pin
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// mapping in cells variable.
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uint32_t check_wires(const Context *ctx) const;
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};
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// Rotate and merge a LUT equation into an array of levels.
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//
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// If a conflict arises, return false and result is in an indeterminate state.
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bool rotate_and_merge_lut_equation(std::vector<LogicLevel> *result, const LutBel &lut_bel,
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const DynamicBitarray<> &old_equation, const std::vector<size_t> &pin_map,
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uint32_t used_pins);
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NEXTPNR_NAMESPACE_END
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#endif /* LUTS_H */
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