140 lines
5.8 KiB
C++
140 lines
5.8 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021 Lofty <dan.ravensloft@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "nextpnr.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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void Arch::create_m10k(int x, int y)
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{
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BelId bel = add_bel(x, y, id_MISTRAL_M10K, id_MISTRAL_M10K);
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add_bel_pin(bel, id_ADDRSTALLA, PORT_IN,
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get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLA, 0));
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add_bel_pin(bel, id_ADDRSTALLB, PORT_IN,
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get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLB, 0));
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for (int z = 0; z < 2; z++) {
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add_bel_pin(bel, id(stringf("BYTEENABLEA[%d]", z)), PORT_IN,
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get_port(CycloneV::M10K, x, y, -1, CycloneV::BYTEENABLEA, z));
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add_bel_pin(bel, id(stringf("BYTEENABLEB[%d]", z)), PORT_IN,
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get_port(CycloneV::M10K, x, y, -1, CycloneV::BYTEENABLEB, z));
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add_bel_pin(bel, id(stringf("ACLR[%d]", z)), PORT_IN,
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get_port(CycloneV::M10K, x, y, -1, CycloneV::ACLR, z));
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add_bel_pin(bel, id(stringf("RDEN[%d]", z)), PORT_IN,
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get_port(CycloneV::M10K, x, y, -1, CycloneV::RDEN, z));
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add_bel_pin(bel, id(stringf("WREN[%d]", z)), PORT_IN,
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get_port(CycloneV::M10K, x, y, -1, CycloneV::WREN, z));
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add_bel_pin(bel, id(stringf("CLKIN[%d]", z)), PORT_IN,
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get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z));
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add_bel_pin(bel, id(stringf("CLKIN[%d]", z+6)), PORT_IN,
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get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z+6));
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}
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for (int z = 0; z < 4; z++) {
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add_bel_pin(bel, id(stringf("ENABLE[%d]", z)), PORT_IN,
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get_port(CycloneV::M10K, x, y, -1, CycloneV::ENABLE, z));
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}
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for (int z = 0; z < 12; z++) {
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add_bel_pin(bel, id(stringf("ADDRA[%d]", z)), PORT_IN,
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get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRA, z));
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add_bel_pin(bel, id(stringf("ADDRB[%d]", z)), PORT_IN,
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get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRB, z));
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}
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for (int z = 0; z < 20; z++) {
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add_bel_pin(bel, id(stringf("DATAAIN[%d]", z)), PORT_IN,
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get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAIN, z));
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add_bel_pin(bel, id(stringf("DATABIN[%d]", z)), PORT_IN,
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get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABIN, z));
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add_bel_pin(bel, id(stringf("DATAAOUT[%d]", z)), PORT_OUT,
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get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAOUT, z));
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add_bel_pin(bel, id(stringf("DATABOUT[%d]", z)), PORT_OUT,
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get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABOUT, z));
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}
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}
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static void assign_lab_pins(Context *ctx, CellInfo *cell)
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{
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auto abits = cell->attrs[id_CFG_ABITS].as_int64();
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auto dbits = cell->attrs[id_CFG_DBITS].as_int64();
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NPNR_ASSERT(abits >= 7 && abits <= 13);
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NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20);
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// Quartus doesn't seem to generate ADDRSTALL[AB], BYTEENABLE[AB][01].
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// It *does* generate ACLR[01] but leaves them unconnected if unused.
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// Enables.
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// RDEN[0] and WREN[1] are left unconnected.
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cell->pin_data[ctx->id("A1EN")].bel_pins = {ctx->id("RDEN[1]")};
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cell->pin_data[ctx->id("B1EN")].bel_pins = {ctx->id("WREN[0]")};
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// Clocks.
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cell->pin_data[ctx->id("CLK1")].bel_pins = {ctx->id("CLKIN[0]")};
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// Enables left unconnected.
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// Address lines.
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int addr_offset = std::max(12 - std::max(abits, int64_t{9}), 0l);
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int bit_offset = 0;
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if (abits == 13) {
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cell->pin_data[ctx->id("A1ADDR[0]")].bel_pins = {ctx->id("DATAAIN[4]")};
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cell->pin_data[ctx->id("B1ADDR[0]")].bel_pins = {ctx->id("DATABIN[19]")};
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bit_offset = 1;
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}
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for (int bit = bit_offset; bit < abits; bit++) {
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cell->pin_data[ctx->id(stringf("A1ADDR[%d]", bit))].bel_pins = {ctx->id(stringf("ADDRA[%d]", bit + addr_offset))};
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cell->pin_data[ctx->id(stringf("B1ADDR[%d]", bit))].bel_pins = {ctx->id(stringf("ADDRB[%d]", bit + addr_offset))};
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}
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// Data lines
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std::vector<int> offsets;
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offsets.push_back(0);
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if (abits >= 10 && dbits <= 10) {
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offsets.push_back(10);
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}
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if (abits >= 11 && dbits <= 5) {
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offsets.push_back(5);
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offsets.push_back(15);
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}
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if (abits >= 12 && dbits <= 2) {
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offsets.push_back(2);
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offsets.push_back(7);
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offsets.push_back(12);
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offsets.push_back(17);
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}
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if (abits == 13 && dbits == 1) {
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offsets.push_back(1);
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offsets.push_back(3);
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offsets.push_back(6);
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offsets.push_back(8);
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offsets.push_back(11);
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offsets.push_back(13);
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offsets.push_back(16);
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offsets.push_back(18);
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}
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for (int bit = 0; bit < dbits; bit++) {
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for (int offset : offsets) {
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cell->pin_data[ctx->id(stringf("A1DATA[%d]", bit))].bel_pins.push_back(ctx->id(stringf("DATAAIN[%d]", bit + offset)));
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}
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}
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for (int bit = 0; bit < dbits; bit++) {
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cell->pin_data[ctx->id(stringf("B1DATA[%d]", bit))].bel_pins = {ctx->id(stringf("DATABOUT[%d]", bit))};
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}
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}
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NEXTPNR_NAMESPACE_END |