694 lines
20 KiB
C++
694 lines
20 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2021 William D. Jones <wjones@wdj-consulting.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef MACHXO2_ARCH_H
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#define MACHXO2_ARCH_H
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#include <cstdint>
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#include "base_arch.h"
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#include "nextpnr_namespaces.h"
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#include "nextpnr_types.h"
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NEXTPNR_NAMESPACE_BEGIN
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/**** Everything in this section must be kept in sync with chipdb.py ****/
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template <typename T> struct RelPtr
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{
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int32_t offset;
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// void set(const T *ptr) {
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// offset = reinterpret_cast<const char*>(ptr) -
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// reinterpret_cast<const char*>(this);
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// }
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const T *get() const { return reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset); }
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const T &operator[](std::size_t index) const { return get()[index]; }
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const T &operator*() const { return *(get()); }
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const T *operator->() const { return get(); }
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};
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// FIXME: All "rel locs" are actually absolute, naming typo in facade_import.
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// Does not affect runtime functionality.
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NPNR_PACKED_STRUCT(struct BelWirePOD {
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LocationPOD rel_wire_loc;
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int32_t wire_index;
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int32_t port;
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int32_t dir; // FIXME: Corresponds to "type" in ECP5.
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});
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NPNR_PACKED_STRUCT(struct BelInfoPOD {
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RelPtr<char> name;
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int32_t type;
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int32_t z;
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int32_t num_bel_wires;
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RelPtr<BelWirePOD> bel_wires;
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});
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NPNR_PACKED_STRUCT(struct PipLocatorPOD {
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LocationPOD rel_loc;
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int32_t index;
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});
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NPNR_PACKED_STRUCT(struct BelPortPOD {
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LocationPOD rel_bel_loc;
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int32_t bel_index;
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int32_t port;
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});
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NPNR_PACKED_STRUCT(struct PipInfoPOD {
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LocationPOD src;
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LocationPOD dst;
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int32_t src_idx;
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int32_t dst_idx;
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int32_t timing_class;
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int16_t tile_type;
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int8_t pip_type;
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int8_t padding;
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});
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NPNR_PACKED_STRUCT(struct WireInfoPOD {
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RelPtr<char> name;
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int32_t tile_wire;
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int32_t num_uphill;
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int32_t num_downhill;
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RelPtr<PipLocatorPOD> pips_uphill;
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RelPtr<PipLocatorPOD> pips_downhill;
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int32_t num_bel_pins;
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RelPtr<BelPortPOD> bel_pins;
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});
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NPNR_PACKED_STRUCT(struct TileTypePOD {
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int32_t num_bels;
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int32_t num_wires;
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int32_t num_pips;
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RelPtr<BelInfoPOD> bel_data;
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RelPtr<WireInfoPOD> wire_data;
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RelPtr<PipInfoPOD> pips_data;
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});
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NPNR_PACKED_STRUCT(struct PackagePinPOD {
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RelPtr<char> name;
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LocationPOD abs_loc;
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int32_t bel_index;
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});
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NPNR_PACKED_STRUCT(struct PackageInfoPOD {
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RelPtr<char> name;
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int32_t num_pins;
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RelPtr<PackagePinPOD> pin_data;
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});
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NPNR_PACKED_STRUCT(struct PIOInfoPOD {
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LocationPOD abs_loc;
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int32_t bel_index;
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RelPtr<char> function_name;
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int16_t bank;
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int16_t dqsgroup;
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});
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NPNR_PACKED_STRUCT(struct TileNamePOD {
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RelPtr<char> name;
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int16_t type_idx;
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int16_t padding;
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});
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NPNR_PACKED_STRUCT(struct TileInfoPOD {
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int32_t num_tiles;
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RelPtr<TileNamePOD> tile_names;
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});
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NPNR_PACKED_STRUCT(struct ChipInfoPOD {
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int32_t width, height;
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int32_t num_tiles;
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int32_t num_packages, num_pios;
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int32_t const_id_count;
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RelPtr<TileTypePOD> tiles;
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RelPtr<RelPtr<char>> tiletype_names;
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RelPtr<PackageInfoPOD> package_info;
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RelPtr<PIOInfoPOD> pio_info;
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RelPtr<TileInfoPOD> tile_info;
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});
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/************************ End of chipdb section. ************************/
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// Iterators
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// Iterate over Bels across tiles.
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struct BelIterator
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{
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const ChipInfoPOD *chip;
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int cursor_index;
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int cursor_tile;
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BelIterator operator++()
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{
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cursor_index++;
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while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].num_bels) {
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cursor_index = 0;
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cursor_tile++;
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}
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return *this;
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}
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BelIterator operator++(int)
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{
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BelIterator prior(*this);
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++(*this);
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return prior;
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}
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bool operator!=(const BelIterator &other) const
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{
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return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile;
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}
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bool operator==(const BelIterator &other) const
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{
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return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile;
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}
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BelId operator*() const
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{
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BelId ret;
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ret.location.x = cursor_tile % chip->width;
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ret.location.y = cursor_tile / chip->width;
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ret.index = cursor_index;
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return ret;
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}
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};
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struct BelRange
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{
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BelIterator b, e;
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BelIterator begin() const { return b; }
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BelIterator end() const { return e; }
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};
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// Iterate over Downstream/Upstream Bels for a Wire.
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struct BelPinIterator
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{
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const BelPortPOD *ptr = nullptr;
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Location wire_loc;
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void operator++() { ptr++; }
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bool operator!=(const BelPinIterator &other) const { return ptr != other.ptr; }
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BelPin operator*() const
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{
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BelPin ret;
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ret.bel.index = ptr->bel_index;
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ret.bel.location = ptr->rel_bel_loc;
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ret.pin.index = ptr->port;
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return ret;
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}
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};
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struct BelPinRange
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{
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BelPinIterator b, e;
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BelPinIterator begin() const { return b; }
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BelPinIterator end() const { return e; }
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};
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// Iterator over Wires across tiles.
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struct WireIterator
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{
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const ChipInfoPOD *chip;
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int cursor_index;
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int cursor_tile;
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WireIterator operator++()
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{
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cursor_index++;
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while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].num_wires) {
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cursor_index = 0;
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cursor_tile++;
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}
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return *this;
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}
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WireIterator operator++(int)
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{
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WireIterator prior(*this);
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++(*this);
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return prior;
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}
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bool operator!=(const WireIterator &other) const
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{
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return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile;
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}
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bool operator==(const WireIterator &other) const
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{
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return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile;
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}
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WireId operator*() const
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{
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WireId ret;
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ret.location.x = cursor_tile % chip->width;
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ret.location.y = cursor_tile / chip->width;
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ret.index = cursor_index;
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return ret;
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}
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};
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struct WireRange
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{
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WireIterator b, e;
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WireIterator begin() const { return b; }
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WireIterator end() const { return e; }
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};
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// Iterator over Pips across tiles.
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struct AllPipIterator
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{
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const ChipInfoPOD *chip;
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int cursor_index;
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int cursor_tile;
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AllPipIterator operator++()
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{
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cursor_index++;
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while (cursor_tile < chip->num_tiles && cursor_index >= chip->tiles[cursor_tile].num_pips) {
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cursor_index = 0;
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cursor_tile++;
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}
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return *this;
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}
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AllPipIterator operator++(int)
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{
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AllPipIterator prior(*this);
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++(*this);
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return prior;
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}
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bool operator!=(const AllPipIterator &other) const
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{
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return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile;
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}
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bool operator==(const AllPipIterator &other) const
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{
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return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile;
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}
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PipId operator*() const
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{
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PipId ret;
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ret.location.x = cursor_tile % chip->width;
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ret.location.y = cursor_tile / chip->width;
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ret.index = cursor_index;
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return ret;
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}
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};
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struct AllPipRange
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{
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AllPipIterator b, e;
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AllPipIterator begin() const { return b; }
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AllPipIterator end() const { return e; }
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};
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// Iterate over Downstream/Upstream Pips for a Wire.
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struct PipIterator
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{
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const PipLocatorPOD *cursor = nullptr;
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Location wire_loc;
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void operator++() { cursor++; }
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bool operator!=(const PipIterator &other) const { return cursor != other.cursor; }
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PipId operator*() const
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{
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PipId ret;
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ret.index = cursor->index;
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ret.location = cursor->rel_loc;
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return ret;
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}
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};
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struct PipRange
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{
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PipIterator b, e;
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PipIterator begin() const { return b; }
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PipIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct ArchArgs
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{
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enum ArchArgsTypes
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{
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NONE,
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LCMXO2_256HC,
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LCMXO2_640HC,
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LCMXO2_1200HC,
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LCMXO2_2000HC,
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LCMXO2_4000HC,
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LCMXO2_7000HC,
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} type = NONE;
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std::string package;
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enum SpeedGrade
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{
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SPEED_1 = 0,
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SPEED_2,
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SPEED_3,
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SPEED_4,
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SPEED_5,
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SPEED_6,
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} speed = SPEED_4;
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};
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struct ArchRanges : BaseArchRanges
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{
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using ArchArgsT = ArchArgs;
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// Bels
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using AllBelsRangeT = BelRange;
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using TileBelsRangeT = BelRange;
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using BelPinsRangeT = std::vector<IdString>;
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// Wires
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using AllWiresRangeT = WireRange;
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using DownhillPipRangeT = PipRange;
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using UphillPipRangeT = PipRange;
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using WireBelPinRangeT = BelPinRange;
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// Pips
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using AllPipsRangeT = AllPipRange;
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};
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struct Arch : BaseArch<ArchRanges>
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{
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const ChipInfoPOD *chip_info;
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const PackageInfoPOD *package_info;
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mutable dict<IdStringList, PipId> pip_by_name;
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// fast access to X and Y IdStrings for building object names
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std::vector<IdString> x_ids, y_ids;
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// inverse of the above for name->object mapping
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dict<IdString, int> id_to_x, id_to_y;
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// Helpers
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template <typename Id> const TileTypePOD *tile_info(Id &id) const
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{
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return &(chip_info->tiles[id.location.y * chip_info->width + id.location.x]);
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}
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int get_bel_flat_index(BelId bel) const
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{
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return (bel.location.y * chip_info->width + bel.location.x) * max_loc_bels + bel.index;
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}
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// ---------------------------------------------------------------
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// Common Arch API. Every arch must provide the following methods.
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// General
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ArchArgs args;
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Arch(ArchArgs args);
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static bool is_available(ArchArgs::ArchArgsTypes chip);
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static std::vector<std::string> get_supported_packages(ArchArgs::ArchArgsTypes chip);
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std::string getChipName() const override;
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// Extra helper
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std::string get_full_chip_name() const;
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IdString archId() const override { return id_machxo2; }
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ArchArgs archArgs() const override { return args; }
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IdString archArgsToId(ArchArgs args) const override;
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static const int max_loc_bels = 20;
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int getGridDimX() const override { return chip_info->width; }
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int getGridDimY() const override { return chip_info->height; }
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int getTileBelDimZ(int x, int y) const override { return max_loc_bels; }
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// TODO: Make more precise? The CENTER MUX having config bits across
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// tiles can complicate this?
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int getTilePipDimZ(int x, int y) const override { return 2; }
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char getNameDelimiter() const override { return '/'; }
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// Bels
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BelId getBelByName(IdStringList name) const override;
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IdStringList getBelName(BelId bel) const override
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{
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NPNR_ASSERT(bel != BelId());
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std::array<IdString, 3> ids{x_ids.at(bel.location.x), y_ids.at(bel.location.y),
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id(tile_info(bel)->bel_data[bel.index].name.get())};
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return IdStringList(ids);
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}
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Loc getBelLocation(BelId bel) const override
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{
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NPNR_ASSERT(bel != BelId());
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Loc loc;
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loc.x = bel.location.x;
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loc.y = bel.location.y;
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loc.z = tile_info(bel)->bel_data[bel.index].z;
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return loc;
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}
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BelId getBelByLocation(Loc loc) const override;
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BelRange getBelsByTile(int x, int y) const override;
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bool getBelGlobalBuf(BelId bel) const override;
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BelRange getBels() const override
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{
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BelRange range;
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range.b.cursor_tile = 0;
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range.b.cursor_index = -1;
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range.b.chip = chip_info;
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++range.b; //-1 and then ++ deals with the case of no Bels in the first tile
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range.e.cursor_tile = chip_info->width * chip_info->height;
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range.e.cursor_index = 0;
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range.e.chip = chip_info;
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return range;
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}
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IdString getBelType(BelId bel) const override
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{
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NPNR_ASSERT(bel != BelId());
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IdString id;
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id.index = tile_info(bel)->bel_data[bel.index].type;
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return id;
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}
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WireId getBelPinWire(BelId bel, IdString pin) const override;
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PortType getBelPinType(BelId bel, IdString pin) const override;
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std::vector<IdString> getBelPins(BelId bel) const override;
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// Package
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BelId getPackagePinBel(const std::string &pin) const;
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// Wires
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WireId getWireByName(IdStringList name) const override;
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IdStringList getWireName(WireId wire) const override
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{
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NPNR_ASSERT(wire != WireId());
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std::array<IdString, 3> ids{x_ids.at(wire.location.x), y_ids.at(wire.location.y),
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id(tile_info(wire)->wire_data[wire.index].name.get())};
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return IdStringList(ids);
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}
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DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0.01); }
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WireRange getWires() const override
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{
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WireRange range;
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range.b.cursor_tile = 0;
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range.b.cursor_index = -1;
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range.b.chip = chip_info;
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++range.b; //-1 and then ++ deals with the case of no wries in the first tile
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range.e.cursor_tile = chip_info->width * chip_info->height;
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range.e.cursor_index = 0;
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range.e.chip = chip_info;
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return range;
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}
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BelPinRange getWireBelPins(WireId wire) const override
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{
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BelPinRange range;
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NPNR_ASSERT(wire != WireId());
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range.b.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.get();
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range.b.wire_loc = wire.location;
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range.e.ptr = range.b.ptr + tile_info(wire)->wire_data[wire.index].num_bel_pins;
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range.e.wire_loc = wire.location;
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return range;
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}
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// Pips
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PipId getPipByName(IdStringList name) const override;
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IdStringList getPipName(PipId pip) const override;
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AllPipRange getPips() const override
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{
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AllPipRange range;
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range.b.cursor_tile = 0;
|
|
range.b.cursor_index = -1;
|
|
range.b.chip = chip_info;
|
|
++range.b; //-1 and then ++ deals with the case of no Bels in the first tile
|
|
range.e.cursor_tile = chip_info->width * chip_info->height;
|
|
range.e.cursor_index = 0;
|
|
range.e.chip = chip_info;
|
|
return range;
|
|
}
|
|
|
|
Loc getPipLocation(PipId pip) const override
|
|
{
|
|
Loc loc;
|
|
loc.x = pip.location.x;
|
|
loc.y = pip.location.y;
|
|
|
|
// FIXME: Some Pip's config bits span across tiles. Will Z
|
|
// be affected by this?
|
|
loc.z = 0;
|
|
return loc;
|
|
}
|
|
|
|
WireId getPipSrcWire(PipId pip) const override
|
|
{
|
|
WireId wire;
|
|
NPNR_ASSERT(pip != PipId());
|
|
wire.index = tile_info(pip)->pips_data[pip.index].src_idx;
|
|
wire.location = tile_info(pip)->pips_data[pip.index].src;
|
|
return wire;
|
|
}
|
|
|
|
WireId getPipDstWire(PipId pip) const override
|
|
{
|
|
WireId wire;
|
|
NPNR_ASSERT(pip != PipId());
|
|
wire.index = tile_info(pip)->pips_data[pip.index].dst_idx;
|
|
wire.location = tile_info(pip)->pips_data[pip.index].dst;
|
|
return wire;
|
|
}
|
|
|
|
DelayQuad getPipDelay(PipId pip) const override { return DelayQuad(0.01); }
|
|
|
|
PipRange getPipsDownhill(WireId wire) const override
|
|
{
|
|
PipRange range;
|
|
NPNR_ASSERT(wire != WireId());
|
|
range.b.cursor = tile_info(wire)->wire_data[wire.index].pips_downhill.get();
|
|
range.b.wire_loc = wire.location;
|
|
range.e.cursor = range.b.cursor + tile_info(wire)->wire_data[wire.index].num_downhill;
|
|
range.e.wire_loc = wire.location;
|
|
return range;
|
|
}
|
|
|
|
PipRange getPipsUphill(WireId wire) const override
|
|
{
|
|
PipRange range;
|
|
NPNR_ASSERT(wire != WireId());
|
|
range.b.cursor = tile_info(wire)->wire_data[wire.index].pips_uphill.get();
|
|
range.b.wire_loc = wire.location;
|
|
range.e.cursor = range.b.cursor + tile_info(wire)->wire_data[wire.index].num_uphill;
|
|
range.e.wire_loc = wire.location;
|
|
return range;
|
|
}
|
|
|
|
// Extra Pip helpers.
|
|
int8_t get_pip_class(PipId pip) const { return tile_info(pip)->pips_data[pip.index].pip_type; }
|
|
|
|
std::string get_pip_tilename(PipId pip) const
|
|
{
|
|
auto &tileloc = chip_info->tile_info[pip.location.y * chip_info->width + pip.location.x];
|
|
for (int i = 0; i < tileloc.num_tiles; i++) {
|
|
if (tileloc.tile_names[i].type_idx == tile_info(pip)->pips_data[pip.index].tile_type)
|
|
return tileloc.tile_names[i].name.get();
|
|
}
|
|
NPNR_ASSERT_FALSE("failed to find Pip tile");
|
|
}
|
|
|
|
// Delay
|
|
delay_t estimateDelay(WireId src, WireId dst) const override;
|
|
delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
|
|
delay_t getDelayEpsilon() const override { return 0.001; }
|
|
delay_t getRipupDelayPenalty() const override { return 0.015; }
|
|
float getDelayNS(delay_t v) const override { return v; }
|
|
|
|
delay_t getDelayFromNS(float ns) const override { return ns; }
|
|
|
|
uint32_t getDelayChecksum(delay_t v) const override { return v; }
|
|
|
|
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
|
|
|
|
// Flow
|
|
bool pack() override;
|
|
bool place() override;
|
|
bool route() override;
|
|
|
|
// Placer
|
|
bool isBelLocationValid(BelId bel) const override;
|
|
|
|
static const std::string defaultPlacer;
|
|
static const std::vector<std::string> availablePlacers;
|
|
static const std::string defaultRouter;
|
|
static const std::vector<std::string> availableRouters;
|
|
|
|
// ---------------------------------------------------------------
|
|
// Internal usage
|
|
bool cells_compatible(const CellInfo **cells, int count) const;
|
|
|
|
std::vector<std::pair<std::string, std::string>> get_tiles_at_location(int row, int col);
|
|
std::string get_tile_by_type_and_loc(int row, int col, std::string type) const
|
|
{
|
|
auto &tileloc = chip_info->tile_info[row * chip_info->width + col];
|
|
for (int i = 0; i < tileloc.num_tiles; i++) {
|
|
if (chip_info->tiletype_names[tileloc.tile_names[i].type_idx].get() == type)
|
|
return tileloc.tile_names[i].name.get();
|
|
}
|
|
NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type " +
|
|
type);
|
|
}
|
|
|
|
std::string get_tile_by_type_and_loc(int row, int col, const std::set<std::string> &type) const
|
|
{
|
|
auto &tileloc = chip_info->tile_info[row * chip_info->width + col];
|
|
for (int i = 0; i < tileloc.num_tiles; i++) {
|
|
if (type.count(chip_info->tiletype_names[tileloc.tile_names[i].type_idx].get()))
|
|
return tileloc.tile_names[i].name.get();
|
|
}
|
|
NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type in set");
|
|
}
|
|
|
|
std::string get_tile_by_type(std::string type) const
|
|
{
|
|
for (int i = 0; i < chip_info->height * chip_info->width; i++) {
|
|
auto &tileloc = chip_info->tile_info[i];
|
|
for (int j = 0; j < tileloc.num_tiles; j++)
|
|
if (chip_info->tiletype_names[tileloc.tile_names[j].type_idx].get() == type)
|
|
return tileloc.tile_names[j].name.get();
|
|
}
|
|
NPNR_ASSERT_FALSE_STR("no tile with type " + type);
|
|
}
|
|
};
|
|
|
|
NEXTPNR_NAMESPACE_END
|
|
|
|
#endif /* MACHXO2_ARCH_H */
|