
This involves very few changes, all typical to WASM ports: * WASM doesn't currently support threads or atomics so those are disabled. * WASM doesn't currently support exceptions so the exception machinery is stubbed out. * WASM doesn't (and can't) have mmap(), so an emulation library is used. That library currently doesn't support MAP_SHARED flags, so MAP_PRIVATE is used instead. There is also an update to bring ECP5 bbasm CMake rules to parity with iCE40 ones, since although it is possible to embed chipdb into nextpnr on WASM, a 200 MB WASM file has very few practical uses. The README is not updated and there is no included toolchain file because at the moment it's not possible to build nextpnr with upstream boost and wasi-libc. Boost requires a patch (merged, will be available in boost 1.74.0), wasi-libc requires a few unmerged patches.
828 lines
27 KiB
C++
828 lines
27 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "nextpnr.h"
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#include <boost/algorithm/string.hpp>
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#include "design_utils.h"
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#include "log.h"
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#include "util.h"
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#if defined(__wasm)
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extern "C" {
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// FIXME: WASI does not currently support exceptions.
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void* __cxa_allocate_exception(size_t thrown_size) throw() {
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return malloc(thrown_size);
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}
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bool __cxa_uncaught_exception() throw();
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void __cxa_throw(void* thrown_exception, struct std::type_info * tinfo, void (*dest)(void*)) {
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std::terminate();
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}
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}
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namespace boost {
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void throw_exception( std::exception const & e ) {
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NEXTPNR_NAMESPACE::log_error("boost::exception(): %s\n", e.what());
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}
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}
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#endif
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NEXTPNR_NAMESPACE_BEGIN
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assertion_failure::assertion_failure(std::string msg, std::string expr_str, std::string filename, int line)
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: runtime_error("Assertion failure: " + msg + " (" + filename + ":" + std::to_string(line) + ")"), msg(msg),
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expr_str(expr_str), filename(filename), line(line)
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{
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log_flush();
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}
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void IdString::set(const BaseCtx *ctx, const std::string &s)
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{
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auto it = ctx->idstring_str_to_idx->find(s);
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if (it == ctx->idstring_str_to_idx->end()) {
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index = ctx->idstring_idx_to_str->size();
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auto insert_rc = ctx->idstring_str_to_idx->insert({s, index});
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ctx->idstring_idx_to_str->push_back(&insert_rc.first->first);
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} else {
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index = it->second;
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}
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}
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const std::string &IdString::str(const BaseCtx *ctx) const { return *ctx->idstring_idx_to_str->at(index); }
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const char *IdString::c_str(const BaseCtx *ctx) const { return str(ctx).c_str(); }
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void IdString::initialize_add(const BaseCtx *ctx, const char *s, int idx)
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{
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NPNR_ASSERT(ctx->idstring_str_to_idx->count(s) == 0);
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NPNR_ASSERT(int(ctx->idstring_idx_to_str->size()) == idx);
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auto insert_rc = ctx->idstring_str_to_idx->insert({s, idx});
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ctx->idstring_idx_to_str->push_back(&insert_rc.first->first);
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}
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TimingConstrObjectId BaseCtx::timingWildcardObject()
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{
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TimingConstrObjectId id;
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id.index = 0;
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return id;
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}
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TimingConstrObjectId BaseCtx::timingClockDomainObject(NetInfo *clockDomain)
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{
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NPNR_ASSERT(clockDomain->clkconstr != nullptr);
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if (clockDomain->clkconstr->domain_tmg_id != TimingConstrObjectId()) {
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return clockDomain->clkconstr->domain_tmg_id;
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} else {
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TimingConstraintObject obj;
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TimingConstrObjectId id;
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id.index = int(constraintObjects.size());
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obj.id = id;
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obj.type = TimingConstraintObject::CLOCK_DOMAIN;
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obj.entity = clockDomain->name;
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clockDomain->clkconstr->domain_tmg_id = id;
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constraintObjects.push_back(obj);
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return id;
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}
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}
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TimingConstrObjectId BaseCtx::timingNetObject(NetInfo *net)
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{
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if (net->tmg_id != TimingConstrObjectId()) {
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return net->tmg_id;
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} else {
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TimingConstraintObject obj;
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TimingConstrObjectId id;
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id.index = int(constraintObjects.size());
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obj.id = id;
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obj.type = TimingConstraintObject::NET;
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obj.entity = net->name;
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constraintObjects.push_back(obj);
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net->tmg_id = id;
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return id;
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}
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}
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TimingConstrObjectId BaseCtx::timingCellObject(CellInfo *cell)
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{
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if (cell->tmg_id != TimingConstrObjectId()) {
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return cell->tmg_id;
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} else {
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TimingConstraintObject obj;
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TimingConstrObjectId id;
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id.index = int(constraintObjects.size());
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obj.id = id;
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obj.type = TimingConstraintObject::CELL;
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obj.entity = cell->name;
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constraintObjects.push_back(obj);
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cell->tmg_id = id;
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return id;
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}
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}
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TimingConstrObjectId BaseCtx::timingPortObject(CellInfo *cell, IdString port)
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{
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if (cell->ports.at(port).tmg_id != TimingConstrObjectId()) {
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return cell->ports.at(port).tmg_id;
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} else {
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TimingConstraintObject obj;
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TimingConstrObjectId id;
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id.index = int(constraintObjects.size());
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obj.id = id;
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obj.type = TimingConstraintObject::CELL_PORT;
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obj.entity = cell->name;
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obj.port = port;
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constraintObjects.push_back(obj);
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cell->ports.at(port).tmg_id = id;
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return id;
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}
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}
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Property::Property() : is_string(false), str(""), intval(0) {}
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Property::Property(int64_t intval, int width) : is_string(false), intval(intval)
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{
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str.reserve(width);
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for (int i = 0; i < width; i++)
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str.push_back((intval & (1ULL << i)) ? S1 : S0);
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}
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Property::Property(const std::string &strval) : is_string(true), str(strval), intval(0xDEADBEEF) {}
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Property::Property(State bit) : is_string(false), str(std::string("") + char(bit)), intval(bit == S1) {}
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void CellInfo::addInput(IdString name)
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{
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ports[name].name = name;
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ports[name].type = PORT_IN;
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}
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void CellInfo::addOutput(IdString name)
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{
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ports[name].name = name;
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ports[name].type = PORT_OUT;
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}
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void CellInfo::addInout(IdString name)
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{
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ports[name].name = name;
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ports[name].type = PORT_INOUT;
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}
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void CellInfo::setParam(IdString name, Property value) { params[name] = value; }
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void CellInfo::unsetParam(IdString name) { params.erase(name); }
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void CellInfo::setAttr(IdString name, Property value) { attrs[name] = value; }
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void CellInfo::unsetAttr(IdString name) { attrs.erase(name); }
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std::string Property::to_string() const
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{
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if (is_string) {
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std::string result = str;
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int state = 0;
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for (char c : str) {
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if (state == 0) {
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if (c == '0' || c == '1' || c == 'x' || c == 'z')
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state = 0;
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else if (c == ' ')
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state = 1;
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else
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state = 2;
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} else if (state == 1 && c != ' ')
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state = 2;
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}
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if (state < 2)
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result += " ";
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return result;
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} else {
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return std::string(str.rbegin(), str.rend());
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}
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}
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Property Property::from_string(const std::string &s)
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{
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Property p;
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size_t cursor = s.find_first_not_of("01xz");
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if (cursor == std::string::npos) {
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p.str = std::string(s.rbegin(), s.rend());
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p.is_string = false;
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p.update_intval();
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} else if (s.find_first_not_of(' ', cursor) == std::string::npos) {
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p = Property(s.substr(0, s.size() - 1));
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} else {
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p = Property(s);
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}
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return p;
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}
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void BaseCtx::addConstraint(std::unique_ptr<TimingConstraint> constr)
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{
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for (auto fromObj : constr->from)
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constrsFrom.emplace(fromObj, constr.get());
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for (auto toObj : constr->to)
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constrsTo.emplace(toObj, constr.get());
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IdString name = constr->name;
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constraints[name] = std::move(constr);
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}
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void BaseCtx::removeConstraint(IdString constrName)
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{
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TimingConstraint *constr = constraints[constrName].get();
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for (auto fromObj : constr->from) {
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auto fromConstrs = constrsFrom.equal_range(fromObj);
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constrsFrom.erase(std::find(fromConstrs.first, fromConstrs.second, std::make_pair(fromObj, constr)));
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}
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for (auto toObj : constr->to) {
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auto toConstrs = constrsFrom.equal_range(toObj);
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constrsFrom.erase(std::find(toConstrs.first, toConstrs.second, std::make_pair(toObj, constr)));
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}
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constraints.erase(constrName);
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}
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const char *BaseCtx::nameOfBel(BelId bel) const
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{
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const Context *ctx = getCtx();
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return ctx->getBelName(bel).c_str(ctx);
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}
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const char *BaseCtx::nameOfWire(WireId wire) const
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{
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const Context *ctx = getCtx();
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return ctx->getWireName(wire).c_str(ctx);
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}
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const char *BaseCtx::nameOfPip(PipId pip) const
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{
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const Context *ctx = getCtx();
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return ctx->getPipName(pip).c_str(ctx);
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}
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const char *BaseCtx::nameOfGroup(GroupId group) const
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{
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const Context *ctx = getCtx();
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return ctx->getGroupName(group).c_str(ctx);
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}
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WireId Context::getNetinfoSourceWire(const NetInfo *net_info) const
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{
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if (net_info->driver.cell == nullptr)
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return WireId();
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auto src_bel = net_info->driver.cell->bel;
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if (src_bel == BelId())
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return WireId();
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IdString driver_port = net_info->driver.port;
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auto driver_port_it = net_info->driver.cell->pins.find(driver_port);
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if (driver_port_it != net_info->driver.cell->pins.end())
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driver_port = driver_port_it->second;
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return getBelPinWire(src_bel, driver_port);
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}
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WireId Context::getNetinfoSinkWire(const NetInfo *net_info, const PortRef &user_info) const
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{
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auto dst_bel = user_info.cell->bel;
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if (dst_bel == BelId())
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return WireId();
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IdString user_port = user_info.port;
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auto user_port_it = user_info.cell->pins.find(user_port);
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if (user_port_it != user_info.cell->pins.end())
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user_port = user_port_it->second;
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return getBelPinWire(dst_bel, user_port);
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}
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delay_t Context::getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &user_info) const
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{
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#ifdef ARCH_ECP5
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if (net_info->is_global)
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return 0;
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#endif
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if (net_info->wires.empty())
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return predictDelay(net_info, user_info);
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WireId src_wire = getNetinfoSourceWire(net_info);
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if (src_wire == WireId())
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return 0;
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WireId dst_wire = getNetinfoSinkWire(net_info, user_info);
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WireId cursor = dst_wire;
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delay_t delay = 0;
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while (cursor != WireId() && cursor != src_wire) {
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auto it = net_info->wires.find(cursor);
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if (it == net_info->wires.end())
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break;
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PipId pip = it->second.pip;
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if (pip == PipId())
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break;
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delay += getPipDelay(pip).maxDelay();
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delay += getWireDelay(cursor).maxDelay();
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cursor = getPipSrcWire(pip);
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}
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if (cursor == src_wire)
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return delay + getWireDelay(src_wire).maxDelay();
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return predictDelay(net_info, user_info);
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}
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static uint32_t xorshift32(uint32_t x)
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{
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x ^= x << 13;
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x ^= x >> 17;
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x ^= x << 5;
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return x;
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}
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uint32_t Context::checksum() const
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{
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uint32_t cksum = xorshift32(123456789);
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uint32_t cksum_nets_sum = 0;
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for (auto &it : nets) {
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auto &ni = *it.second;
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uint32_t x = 123456789;
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x = xorshift32(x + xorshift32(it.first.index));
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x = xorshift32(x + xorshift32(ni.name.index));
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if (ni.driver.cell)
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x = xorshift32(x + xorshift32(ni.driver.cell->name.index));
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x = xorshift32(x + xorshift32(ni.driver.port.index));
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x = xorshift32(x + xorshift32(getDelayChecksum(ni.driver.budget)));
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for (auto &u : ni.users) {
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if (u.cell)
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x = xorshift32(x + xorshift32(u.cell->name.index));
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x = xorshift32(x + xorshift32(u.port.index));
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x = xorshift32(x + xorshift32(getDelayChecksum(u.budget)));
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}
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uint32_t attr_x_sum = 0;
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for (auto &a : ni.attrs) {
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uint32_t attr_x = 123456789;
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attr_x = xorshift32(attr_x + xorshift32(a.first.index));
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for (char ch : a.second.str)
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attr_x = xorshift32(attr_x + xorshift32((int)ch));
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attr_x_sum += attr_x;
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}
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x = xorshift32(x + xorshift32(attr_x_sum));
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uint32_t wire_x_sum = 0;
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for (auto &w : ni.wires) {
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uint32_t wire_x = 123456789;
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wire_x = xorshift32(wire_x + xorshift32(getWireChecksum(w.first)));
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wire_x = xorshift32(wire_x + xorshift32(getPipChecksum(w.second.pip)));
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wire_x = xorshift32(wire_x + xorshift32(int(w.second.strength)));
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wire_x_sum += wire_x;
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}
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x = xorshift32(x + xorshift32(wire_x_sum));
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cksum_nets_sum += x;
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}
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cksum = xorshift32(cksum + xorshift32(cksum_nets_sum));
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uint32_t cksum_cells_sum = 0;
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for (auto &it : cells) {
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auto &ci = *it.second;
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uint32_t x = 123456789;
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x = xorshift32(x + xorshift32(it.first.index));
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x = xorshift32(x + xorshift32(ci.name.index));
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x = xorshift32(x + xorshift32(ci.type.index));
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uint32_t port_x_sum = 0;
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for (auto &p : ci.ports) {
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uint32_t port_x = 123456789;
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port_x = xorshift32(port_x + xorshift32(p.first.index));
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port_x = xorshift32(port_x + xorshift32(p.second.name.index));
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if (p.second.net)
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port_x = xorshift32(port_x + xorshift32(p.second.net->name.index));
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port_x = xorshift32(port_x + xorshift32(p.second.type));
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port_x_sum += port_x;
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}
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x = xorshift32(x + xorshift32(port_x_sum));
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uint32_t attr_x_sum = 0;
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|
for (auto &a : ci.attrs) {
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|
uint32_t attr_x = 123456789;
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attr_x = xorshift32(attr_x + xorshift32(a.first.index));
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for (char ch : a.second.str)
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attr_x = xorshift32(attr_x + xorshift32((int)ch));
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attr_x_sum += attr_x;
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}
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x = xorshift32(x + xorshift32(attr_x_sum));
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uint32_t param_x_sum = 0;
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for (auto &p : ci.params) {
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uint32_t param_x = 123456789;
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param_x = xorshift32(param_x + xorshift32(p.first.index));
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for (char ch : p.second.str)
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param_x = xorshift32(param_x + xorshift32((int)ch));
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param_x_sum += param_x;
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}
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x = xorshift32(x + xorshift32(param_x_sum));
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x = xorshift32(x + xorshift32(getBelChecksum(ci.bel)));
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x = xorshift32(x + xorshift32(ci.belStrength));
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uint32_t pin_x_sum = 0;
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for (auto &a : ci.pins) {
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uint32_t pin_x = 123456789;
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pin_x = xorshift32(pin_x + xorshift32(a.first.index));
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pin_x = xorshift32(pin_x + xorshift32(a.second.index));
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pin_x_sum += pin_x;
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}
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x = xorshift32(x + xorshift32(pin_x_sum));
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cksum_cells_sum += x;
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}
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cksum = xorshift32(cksum + xorshift32(cksum_cells_sum));
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return cksum;
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}
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|
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void Context::check() const
|
|
{
|
|
for (auto &n : nets) {
|
|
auto ni = n.second.get();
|
|
NPNR_ASSERT(n.first == ni->name);
|
|
for (auto &w : ni->wires) {
|
|
NPNR_ASSERT(ni == getBoundWireNet(w.first));
|
|
if (w.second.pip != PipId()) {
|
|
NPNR_ASSERT(w.first == getPipDstWire(w.second.pip));
|
|
NPNR_ASSERT(ni == getBoundPipNet(w.second.pip));
|
|
}
|
|
}
|
|
if (ni->driver.cell != nullptr)
|
|
NPNR_ASSERT(ni->driver.cell->ports.at(ni->driver.port).net == ni);
|
|
for (auto user : ni->users) {
|
|
NPNR_ASSERT(user.cell->ports.at(user.port).net == ni);
|
|
}
|
|
}
|
|
|
|
for (auto w : getWires()) {
|
|
auto ni = getBoundWireNet(w);
|
|
if (ni != nullptr) {
|
|
NPNR_ASSERT(ni->wires.count(w));
|
|
}
|
|
}
|
|
|
|
for (auto &c : cells) {
|
|
auto ci = c.second.get();
|
|
NPNR_ASSERT(c.first == ci->name);
|
|
if (ci->bel != BelId())
|
|
NPNR_ASSERT(getBoundBelCell(c.second->bel) == ci);
|
|
for (auto &port : c.second->ports) {
|
|
NetInfo *net = port.second.net;
|
|
if (net != nullptr) {
|
|
NPNR_ASSERT(nets.find(net->name) != nets.end());
|
|
if (port.second.type == PORT_OUT) {
|
|
NPNR_ASSERT(net->driver.cell == c.second.get() && net->driver.port == port.first);
|
|
} else if (port.second.type == PORT_IN) {
|
|
NPNR_ASSERT(std::count_if(net->users.begin(), net->users.end(), [&](const PortRef &pr) {
|
|
return pr.cell == c.second.get() && pr.port == port.first;
|
|
}) == 1);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void BaseCtx::addClock(IdString net, float freq)
|
|
{
|
|
std::unique_ptr<ClockConstraint> cc(new ClockConstraint());
|
|
cc->period = getCtx()->getDelayFromNS(1000 / freq);
|
|
cc->high = getCtx()->getDelayFromNS(500 / freq);
|
|
cc->low = getCtx()->getDelayFromNS(500 / freq);
|
|
if (!net_aliases.count(net)) {
|
|
log_warning("net '%s' does not exist in design, ignoring clock constraint\n", net.c_str(this));
|
|
} else {
|
|
getNetByAlias(net)->clkconstr = std::move(cc);
|
|
log_info("constraining clock net '%s' to %.02f MHz\n", net.c_str(this), freq);
|
|
}
|
|
}
|
|
|
|
void BaseCtx::createRectangularRegion(IdString name, int x0, int y0, int x1, int y1)
|
|
{
|
|
std::unique_ptr<Region> new_region(new Region());
|
|
new_region->name = name;
|
|
new_region->constr_bels = true;
|
|
new_region->constr_pips = false;
|
|
new_region->constr_wires = false;
|
|
for (int x = x0; x <= x1; x++) {
|
|
for (int y = y0; y <= y1; y++) {
|
|
for (auto bel : getCtx()->getBelsByTile(x, y))
|
|
new_region->bels.insert(bel);
|
|
}
|
|
}
|
|
region[name] = std::move(new_region);
|
|
}
|
|
void BaseCtx::addBelToRegion(IdString name, BelId bel) { region[name]->bels.insert(bel); }
|
|
void BaseCtx::constrainCellToRegion(IdString cell, IdString region_name)
|
|
{
|
|
// Support hierarchical cells as well as leaf ones
|
|
if (hierarchy.count(cell)) {
|
|
auto &hc = hierarchy.at(cell);
|
|
for (auto &lc : hc.leaf_cells)
|
|
constrainCellToRegion(lc.second, region_name);
|
|
for (auto &hsc : hc.hier_cells)
|
|
constrainCellToRegion(hsc.second, region_name);
|
|
}
|
|
if (cells.count(cell))
|
|
cells.at(cell)->region = region[region_name].get();
|
|
}
|
|
DecalXY BaseCtx::constructDecalXY(DecalId decal, float x, float y)
|
|
{
|
|
DecalXY dxy;
|
|
dxy.decal = decal;
|
|
dxy.x = x;
|
|
dxy.y = y;
|
|
return dxy;
|
|
}
|
|
|
|
void BaseCtx::archInfoToAttributes()
|
|
{
|
|
for (auto &cell : cells) {
|
|
auto ci = cell.second.get();
|
|
if (ci->bel != BelId()) {
|
|
if (ci->attrs.find(id("BEL")) != ci->attrs.end()) {
|
|
ci->attrs.erase(ci->attrs.find(id("BEL")));
|
|
}
|
|
ci->attrs[id("NEXTPNR_BEL")] = getCtx()->getBelName(ci->bel).str(this);
|
|
ci->attrs[id("BEL_STRENGTH")] = (int)ci->belStrength;
|
|
}
|
|
if (ci->constr_x != ci->UNCONSTR)
|
|
ci->attrs[id("CONSTR_X")] = ci->constr_x;
|
|
if (ci->constr_y != ci->UNCONSTR)
|
|
ci->attrs[id("CONSTR_Y")] = ci->constr_y;
|
|
if (ci->constr_z != ci->UNCONSTR) {
|
|
ci->attrs[id("CONSTR_Z")] = ci->constr_z;
|
|
ci->attrs[id("CONSTR_ABS_Z")] = ci->constr_abs_z ? 1 : 0;
|
|
}
|
|
if (ci->constr_parent != nullptr)
|
|
ci->attrs[id("CONSTR_PARENT")] = ci->constr_parent->name.str(this);
|
|
if (!ci->constr_children.empty()) {
|
|
std::string constr = "";
|
|
for (auto &item : ci->constr_children) {
|
|
if (!constr.empty())
|
|
constr += std::string(";");
|
|
constr += item->name.c_str(this);
|
|
}
|
|
ci->attrs[id("CONSTR_CHILDREN")] = constr;
|
|
}
|
|
}
|
|
for (auto &net : getCtx()->nets) {
|
|
auto ni = net.second.get();
|
|
std::string routing;
|
|
bool first = true;
|
|
for (auto &item : ni->wires) {
|
|
if (!first)
|
|
routing += ";";
|
|
routing += getCtx()->getWireName(item.first).c_str(this);
|
|
routing += ";";
|
|
if (item.second.pip != PipId())
|
|
routing += getCtx()->getPipName(item.second.pip).c_str(this);
|
|
routing += ";" + std::to_string(item.second.strength);
|
|
first = false;
|
|
}
|
|
ni->attrs[id("ROUTING")] = routing;
|
|
}
|
|
}
|
|
|
|
void BaseCtx::attributesToArchInfo()
|
|
{
|
|
for (auto &cell : cells) {
|
|
auto ci = cell.second.get();
|
|
auto val = ci->attrs.find(id("NEXTPNR_BEL"));
|
|
if (val != ci->attrs.end()) {
|
|
auto str = ci->attrs.find(id("BEL_STRENGTH"));
|
|
PlaceStrength strength = PlaceStrength::STRENGTH_USER;
|
|
if (str != ci->attrs.end())
|
|
strength = (PlaceStrength)str->second.as_int64();
|
|
|
|
BelId b = getCtx()->getBelByName(id(val->second.as_string()));
|
|
getCtx()->bindBel(b, ci, strength);
|
|
}
|
|
|
|
val = ci->attrs.find(id("CONSTR_PARENT"));
|
|
if (val != ci->attrs.end()) {
|
|
auto parent = cells.find(id(val->second.str));
|
|
if (parent != cells.end())
|
|
ci->constr_parent = parent->second.get();
|
|
else
|
|
continue;
|
|
}
|
|
|
|
val = ci->attrs.find(id("CONSTR_X"));
|
|
if (val != ci->attrs.end())
|
|
ci->constr_x = val->second.as_int64();
|
|
|
|
val = ci->attrs.find(id("CONSTR_Y"));
|
|
if (val != ci->attrs.end())
|
|
ci->constr_y = val->second.as_int64();
|
|
|
|
val = ci->attrs.find(id("CONSTR_Z"));
|
|
if (val != ci->attrs.end())
|
|
ci->constr_z = val->second.as_int64();
|
|
|
|
val = ci->attrs.find(id("CONSTR_ABS_Z"));
|
|
if (val != ci->attrs.end())
|
|
ci->constr_abs_z = val->second.as_int64() == 1;
|
|
|
|
val = ci->attrs.find(id("CONSTR_PARENT"));
|
|
if (val != ci->attrs.end()) {
|
|
auto parent = cells.find(id(val->second.as_string()));
|
|
if (parent != cells.end())
|
|
ci->constr_parent = parent->second.get();
|
|
}
|
|
val = ci->attrs.find(id("CONSTR_CHILDREN"));
|
|
if (val != ci->attrs.end()) {
|
|
std::vector<std::string> strs;
|
|
auto children = val->second.as_string();
|
|
boost::split(strs, children, boost::is_any_of(";"));
|
|
for (auto val : strs) {
|
|
if (cells.count(id(val.c_str())))
|
|
ci->constr_children.push_back(cells.find(id(val.c_str()))->second.get());
|
|
}
|
|
}
|
|
}
|
|
for (auto &net : getCtx()->nets) {
|
|
auto ni = net.second.get();
|
|
auto val = ni->attrs.find(id("ROUTING"));
|
|
if (val != ni->attrs.end()) {
|
|
std::vector<std::string> strs;
|
|
auto routing = val->second.as_string();
|
|
boost::split(strs, routing, boost::is_any_of(";"));
|
|
for (size_t i = 0; i < strs.size() / 3; i++) {
|
|
std::string wire = strs[i * 3];
|
|
std::string pip = strs[i * 3 + 1];
|
|
PlaceStrength strength = (PlaceStrength)std::stoi(strs[i * 3 + 2]);
|
|
if (pip.empty())
|
|
getCtx()->bindWire(getCtx()->getWireByName(id(wire)), ni, strength);
|
|
else
|
|
getCtx()->bindPip(getCtx()->getPipByName(id(pip)), ni, strength);
|
|
}
|
|
}
|
|
}
|
|
getCtx()->assignArchInfo();
|
|
}
|
|
|
|
NetInfo *BaseCtx::createNet(IdString name)
|
|
{
|
|
NPNR_ASSERT(!nets.count(name));
|
|
NPNR_ASSERT(!net_aliases.count(name));
|
|
std::unique_ptr<NetInfo> net{new NetInfo};
|
|
net->name = name;
|
|
net_aliases[name] = name;
|
|
NetInfo *ptr = net.get();
|
|
nets[name] = std::move(net);
|
|
refreshUi();
|
|
return ptr;
|
|
}
|
|
|
|
void BaseCtx::connectPort(IdString net, IdString cell, IdString port)
|
|
{
|
|
NetInfo *net_info = getNetByAlias(net);
|
|
CellInfo *cell_info = cells.at(cell).get();
|
|
connect_port(getCtx(), net_info, cell_info, port);
|
|
}
|
|
|
|
void BaseCtx::disconnectPort(IdString cell, IdString port)
|
|
{
|
|
CellInfo *cell_info = cells.at(cell).get();
|
|
disconnect_port(getCtx(), cell_info, port);
|
|
}
|
|
|
|
void BaseCtx::ripupNet(IdString name)
|
|
{
|
|
NetInfo *net_info = getNetByAlias(name);
|
|
std::vector<WireId> to_unbind;
|
|
for (auto &wire : net_info->wires)
|
|
to_unbind.push_back(wire.first);
|
|
for (auto &unbind : to_unbind)
|
|
getCtx()->unbindWire(unbind);
|
|
}
|
|
void BaseCtx::lockNetRouting(IdString name)
|
|
{
|
|
NetInfo *net_info = getNetByAlias(name);
|
|
for (auto &wire : net_info->wires)
|
|
wire.second.strength = STRENGTH_USER;
|
|
}
|
|
|
|
CellInfo *BaseCtx::createCell(IdString name, IdString type)
|
|
{
|
|
NPNR_ASSERT(!cells.count(name));
|
|
std::unique_ptr<CellInfo> cell{new CellInfo};
|
|
cell->name = name;
|
|
cell->type = type;
|
|
CellInfo *ptr = cell.get();
|
|
cells[name] = std::move(cell);
|
|
refreshUi();
|
|
return ptr;
|
|
}
|
|
|
|
void BaseCtx::copyBelPorts(IdString cell, BelId bel)
|
|
{
|
|
CellInfo *cell_info = cells.at(cell).get();
|
|
for (auto pin : getCtx()->getBelPins(bel)) {
|
|
cell_info->ports[pin].name = pin;
|
|
cell_info->ports[pin].type = getCtx()->getBelPinType(bel, pin);
|
|
}
|
|
}
|
|
|
|
namespace {
|
|
struct FixupHierarchyWorker
|
|
{
|
|
FixupHierarchyWorker(Context *ctx) : ctx(ctx){};
|
|
Context *ctx;
|
|
void run()
|
|
{
|
|
trim_hierarchy(ctx->top_module);
|
|
rebuild_hierarchy();
|
|
};
|
|
// Remove cells and nets that no longer exist in the netlist
|
|
std::vector<IdString> todelete_cells, todelete_nets;
|
|
void trim_hierarchy(IdString path)
|
|
{
|
|
auto &h = ctx->hierarchy.at(path);
|
|
todelete_cells.clear();
|
|
todelete_nets.clear();
|
|
for (auto &lc : h.leaf_cells) {
|
|
if (!ctx->cells.count(lc.second))
|
|
todelete_cells.push_back(lc.first);
|
|
}
|
|
for (auto &n : h.nets)
|
|
if (!ctx->nets.count(n.second))
|
|
todelete_nets.push_back(n.first);
|
|
for (auto tdc : todelete_cells) {
|
|
h.leaf_cells_by_gname.erase(h.leaf_cells.at(tdc));
|
|
h.leaf_cells.erase(tdc);
|
|
}
|
|
for (auto tdn : todelete_nets) {
|
|
h.nets_by_gname.erase(h.nets.at(tdn));
|
|
h.nets.erase(tdn);
|
|
}
|
|
for (auto &sc : h.hier_cells)
|
|
trim_hierarchy(sc.second);
|
|
}
|
|
|
|
IdString construct_local_name(HierarchicalCell &hc, IdString global_name, bool is_cell)
|
|
{
|
|
std::string gn = global_name.str(ctx);
|
|
auto dp = gn.find_last_of('.');
|
|
if (dp != std::string::npos)
|
|
gn = gn.substr(dp + 1);
|
|
IdString name = ctx->id(gn);
|
|
// Make sure name is unique
|
|
int adder = 0;
|
|
while (is_cell ? hc.leaf_cells.count(name) : hc.nets.count(name)) {
|
|
++adder;
|
|
name = ctx->id(gn + "$" + std::to_string(adder));
|
|
}
|
|
return name;
|
|
}
|
|
|
|
// Update hierarchy structure for nets and cells that have hiercell set
|
|
void rebuild_hierarchy()
|
|
{
|
|
for (auto cell : sorted(ctx->cells)) {
|
|
CellInfo *ci = cell.second;
|
|
if (ci->hierpath == IdString())
|
|
ci->hierpath = ctx->top_module;
|
|
auto &hc = ctx->hierarchy.at(ci->hierpath);
|
|
if (hc.leaf_cells_by_gname.count(ci->name))
|
|
continue; // already known
|
|
IdString local_name = construct_local_name(hc, ci->name, true);
|
|
hc.leaf_cells_by_gname[ci->name] = local_name;
|
|
hc.leaf_cells[local_name] = ci->name;
|
|
}
|
|
}
|
|
};
|
|
} // namespace
|
|
|
|
void Context::fixupHierarchy() { FixupHierarchyWorker(this).run(); }
|
|
|
|
NEXTPNR_NAMESPACE_END
|