144 lines
5.0 KiB
C++
144 lines
5.0 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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* Copyright (C) 2018 David Shah <david@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "cells.h"
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#include "nextpnr.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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bool Arch::logicCellsCompatible(const std::vector<const CellInfo *> &cells) const
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{
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bool dffs_exist = false, dffs_neg = false;
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const NetInfo *cen = nullptr, *clk = nullptr, *sr = nullptr;
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int locals_count = 0;
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for (auto cell : cells) {
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if (bool_or_default(cell->params, id_dff_en)) {
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if (!dffs_exist) {
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dffs_exist = true;
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cen = get_net_or_empty(cell, id_cen);
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clk = get_net_or_empty(cell, id_clk);
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sr = get_net_or_empty(cell, id_sr);
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if (!isGlobalNet(cen) && cen != nullptr)
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locals_count++;
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if (!isGlobalNet(clk) && clk != nullptr)
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locals_count++;
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if (!isGlobalNet(sr) && sr != nullptr)
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locals_count++;
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if (bool_or_default(cell->params, id_neg_clk)) {
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dffs_neg = true;
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}
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} else {
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if (cen != get_net_or_empty(cell, id_cen))
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return false;
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if (clk != get_net_or_empty(cell, id_clk))
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return false;
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if (sr != get_net_or_empty(cell, id_sr))
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return false;
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if (dffs_neg != bool_or_default(cell->params, id_neg_clk))
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return false;
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}
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}
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const NetInfo *i0 = get_net_or_empty(cell, id_i0), *i1 = get_net_or_empty(cell, id_i1),
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*i2 = get_net_or_empty(cell, id_i2), *i3 = get_net_or_empty(cell, id_i3);
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if (i0 != nullptr)
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locals_count++;
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if (i1 != nullptr)
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locals_count++;
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if (i2 != nullptr)
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locals_count++;
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if (i3 != nullptr)
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locals_count++;
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}
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return locals_count <= 32;
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}
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bool Arch::isBelLocationValid(BelId bel) const
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{
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if (getBelType(bel) == TYPE_ICESTORM_LC) {
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std::vector<const CellInfo *> bel_cells;
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for (auto bel_other : getBelsAtSameTile(bel)) {
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IdString cell_other = getBoundBelCellUnlocked(bel_other);
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if (cell_other != IdString()) {
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const CellInfo *ci_other = cells.at(cell_other).get();
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bel_cells.push_back(ci_other);
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}
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}
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return logicCellsCompatible(bel_cells);
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} else {
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IdString cellId = getBoundBelCellUnlocked(bel);
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if (cellId == IdString())
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return true;
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else
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return isValidBelForCell(cells.at(cellId).get(), bel);
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}
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}
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bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
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{
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if (cell->type == id_icestorm_lc) {
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NPNR_ASSERT(getBelType(bel) == TYPE_ICESTORM_LC);
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std::vector<const CellInfo *> bel_cells;
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for (auto bel_other : getBelsAtSameTile(bel)) {
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IdString cell_other = getBoundBelCellUnlocked(bel_other);
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if (cell_other != IdString() && bel_other != bel) {
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const CellInfo *ci_other = cells.at(cell_other).get();
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bel_cells.push_back(ci_other);
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}
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}
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bel_cells.push_back(cell);
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return logicCellsCompatible(bel_cells);
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} else if (cell->type == id_sb_io) {
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return getBelPackagePin(bel) != "";
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} else if (cell->type == id_sb_gb) {
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bool is_reset = false, is_cen = false;
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NPNR_ASSERT(cell->ports.at(id_glb_buf_out).net != nullptr);
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for (auto user : cell->ports.at(id_glb_buf_out).net->users) {
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if (is_reset_port(this, user))
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is_reset = true;
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if (is_enable_port(this, user))
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is_cen = true;
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}
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IdString glb_net = getWireName(getWireBelPin(bel, PIN_GLOBAL_BUFFER_OUTPUT));
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int glb_id = std::stoi(std::string("") + glb_net.str(this).back());
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if (is_reset && is_cen)
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return false;
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else if (is_reset)
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return (glb_id % 2) == 0;
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else if (is_cen)
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return (glb_id % 2) == 1;
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else
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return true;
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} else {
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// TODO: IO cell clock checks
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return true;
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}
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}
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NEXTPNR_NAMESPACE_END
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