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49f8620ac9
nextpnr/himbaechel/uarch/gowin
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YRabbit 49f8620ac9 gowin: Himbaechel. Implement PLLs 
- The global router is modified to work out the routing of PLL outputs and inputs;
- Added API function to change wire type after its creation - there was
  a need to unify all wires included in the node at the stage of node
  creation, when all wires have already been created.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-08-31 08:28:09 +02:00
..
constids.inc gowin: Himbaechel. Implement PLLs 2023-08-31 08:28:09 +02:00
cst.cc gowin: Himbaechel. Add constraint file processing. 2023-08-31 08:28:09 +02:00
cst.h gowin: Himbaechel. Add constraint file processing. 2023-08-31 08:28:09 +02:00
globals.cc gowin: Himbaechel. Implement PLLs 2023-08-31 08:28:09 +02:00
globals.h gowin: Himbaechel. Add a clock router. 2023-08-31 08:28:09 +02:00
gowin_arch_gen.py gowin: Himbaechel. Implement PLLs 2023-08-31 08:28:09 +02:00
gowin_utils.cc gowin: Himbaechel. Use pin functions info 2023-08-31 08:28:09 +02:00
gowin_utils.h gowin: Himbaechel. Use pin functions info 2023-08-31 08:28:09 +02:00
gowin.cc gowin: Himbaechel. Use pin functions info 2023-08-31 08:28:09 +02:00
gowin.h gowin: Himbaechel. Implement PLLs 2023-08-31 08:28:09 +02:00
pack.cc gowin: Himbaechel. Implement PLLs 2023-08-31 08:28:09 +02:00
pack.h gowin: Himbaechel. Add ALU. 2023-08-31 08:28:09 +02:00