49f8620ac9
- The global router is modified to work out the routing of PLL outputs and inputs; - Added API function to change wire type after its creation - there was a need to unify all wires included in the node at the stage of node creation, when all wires have already been created. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
498 lines
20 KiB
Python
498 lines
20 KiB
Python
from os import path
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import sys
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import importlib.resources
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import pickle
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import gzip
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import re
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import argparse
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sys.path.append(path.join(path.dirname(__file__), "../.."))
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from himbaechel_dbgen.chip import *
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from apycula import chipdb
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# Z of the bels
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# sync with C++ part!
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LUT0_Z = 0 # z(DFFx) = z(LUTx) + 1
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LUT7_Z = 14
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MUX20_Z = 16
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MUX21_Z = 18
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MUX23_Z = 22
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MUX27_Z = 29
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ALU0_Z = 30 # : 35, 6 ALUs
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RAMW_Z = 36 # RAM16SDP4
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PLL_Z = 275
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GSR_Z = 276
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VCC_Z = 277
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GND_Z = 278
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@dataclass
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class TileExtraData(BBAStruct):
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tile_class: IdString # The general functionality of the slightly different tiles,
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# let's say the behavior of LUT+DFF in the tiles are completely identical,
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# but one of them also contains clock-wire switches,
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# then we assign them to the same LOGIC class.
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def serialise_lists(self, context: str, bba: BBAWriter):
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pass
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def serialise(self, context: str, bba: BBAWriter):
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bba.u32(self.tile_class.index)
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created_tiletypes = set()
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# u-turn at the rim
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uturnlut = {'N': 'S', 'S': 'N', 'E': 'W', 'W': 'E'}
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def uturn(db: chipdb, x: int, y: int, wire: str):
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m = re.match(r"([NESW])([128]\d)(\d)", wire)
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if m:
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direction, num, segment = m.groups()
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# wires wrap around the edges
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# assumes 0-based indexes
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if y < 0:
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y = -1 - y
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direction = uturnlut[direction]
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if x < 0:
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x = -1 - x
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direction = uturnlut[direction]
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if y > db.rows - 1:
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y = 2 * db.rows - 1 - y
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direction = uturnlut[direction]
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if x > db.cols - 1:
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x = 2 * db.cols - 1 - x
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direction = uturnlut[direction]
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wire = f'{direction}{num}{segment}'
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return (x, y, wire)
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def create_nodes(chip: Chip, db: chipdb):
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# : (x, y)
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dirs = { 'N': (0, -1), 'S': (0, 1), 'W': (-1, 0), 'E': (1, 0) }
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X = db.cols
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Y = db.rows
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global_nodes = {}
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for y in range(Y):
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for x in range(X):
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nodes = []
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tt = chip.tile_type_at(x, y)
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extra_tile_data = tt.extra_data
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# SN and EW
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for i in [1, 2]:
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nodes.append([NodeWire(x, y, f'SN{i}0'),
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NodeWire(*uturn(db, x, y - 1, f'N1{i}1')),
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NodeWire(*uturn(db, x, y + 1, f'S1{i}1'))])
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nodes.append([NodeWire(x, y, f'EW{i}0'),
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NodeWire(*uturn(db, x - 1, y, f'W1{i}1')),
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NodeWire(*uturn(db, x + 1, y, f'E1{i}1'))])
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for d, offs in dirs.items():
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# 1-hop
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for i in [0, 3]:
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nodes.append([NodeWire(x, y, f'{d}1{i}0'),
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NodeWire(*uturn(db, x + offs[0], y + offs[1], f'{d}1{i}1'))])
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# 2-hop
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for i in range(8):
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nodes.append([NodeWire(x, y, f'{d}2{i}0'),
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NodeWire(*uturn(db, x + offs[0], y + offs[1], f'{d}2{i}1')),
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NodeWire(*uturn(db, x + offs[0] * 2, y + offs[1] * 2, f'{d}2{i}2'))])
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# 4-hop
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for i in range(4):
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nodes.append([NodeWire(x, y, f'{d}8{i}0'),
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NodeWire(*uturn(db, x + offs[0] * 4, y + offs[1] * 4, f'{d}8{i}4')),
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NodeWire(*uturn(db, x + offs[0] * 8, y + offs[1] * 8, f'{d}8{i}8'))])
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# I0 for MUX2_LUT8
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if (x < X - 1 and extra_tile_data.tile_class == chip.strs.id('LOGIC')
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and chip.tile_type_at(x + 1, y).extra_data.tile_class == chip.strs.id('LOGIC')):
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nodes.append([NodeWire(x, y, 'OF30'),
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NodeWire(x + 1, y, 'OF3')])
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# ALU
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if extra_tile_data.tile_class == chip.strs.id('LOGIC'):
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# local carry chain
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for i in range(5):
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nodes.append([NodeWire(x, y, f'COUT{i}'),
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NodeWire(x, y, f'CIN{i + 1}')]);
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# gobal carry chain
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if x > 1 and chip.tile_type_at(x - 1, y).extra_data.tile_class == chip.strs.id('LOGIC'):
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nodes.append([NodeWire(x, y, f'CIN0'),
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NodeWire(x - 1, y, f'COUT5')])
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for node in nodes:
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chip.add_node(node)
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# VCC and VSS sources in the all tiles
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global_nodes.setdefault('GND', []).append(NodeWire(x, y, 'VSS'))
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global_nodes.setdefault('VCC', []).append(NodeWire(x, y, 'VCC'))
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# add nodes from the apicula db
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for node_name, node_hdr in db.nodes.items():
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wire_type, node = node_hdr
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for y, x, wire in node:
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if wire_type:
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chip.tile_type_at(x, y).set_wire_type(wire, wire_type)
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new_node = NodeWire(x, y, wire)
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gl_nodes = global_nodes.setdefault(node_name, [])
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if new_node not in gl_nodes:
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gl_nodes.append(NodeWire(x, y, wire))
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for name, node in global_nodes.items():
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chip.add_node(node)
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# About X and Y as parameters - in some cases, the type of manufacturer's tile
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# is not different, but some wires are not physically present, that is, routing
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# depends on the location of otherwise identical tiles. There are many options
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# for taking this into account, but for now we make a distinction here, by
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# coordinates.
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def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
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def get_wire_type(name):
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if name in {'XD0', 'XD1', 'XD2', 'XD3', 'XD4', 'XD5',}:
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return "X0"
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return ""
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for dst, srcs in db.grid[y][x].pips.items():
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if not tt.has_wire(dst):
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tt.create_wire(dst, get_wire_type(dst))
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for src in srcs.keys():
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if not tt.has_wire(src):
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tt.create_wire(src, get_wire_type(src))
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tt.create_pip(src, dst)
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# clock wires
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for dst, srcs in db.grid[y][x].clock_pips.items():
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if not tt.has_wire(dst):
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tt.create_wire(dst, "GLOBAL_CLK")
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for src in srcs.keys():
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if not tt.has_wire(src):
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tt.create_wire(src, "GLOBAL_CLK")
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tt.create_pip(src, dst)
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def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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if ttyp in created_tiletypes:
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return ttyp, None
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typename = "NULL"
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tt = chip.create_tile_type(f"{typename}_{ttyp}")
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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create_switch_matrix(tt, db, x, y)
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return (ttyp, tt)
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# responsible nodes, there will be IO banks, configuration, etc.
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def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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if ttyp in created_tiletypes:
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return ttyp, None
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typename = "CORNER"
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tt = chip.create_tile_type(f"{typename}_{ttyp}")
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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if x == 0 and y == 0:
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# GND is the logic low level generator
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tt.create_wire('VSS', 'GND')
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gnd = tt.create_bel('GND', 'GND', z = GND_Z)
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tt.add_bel_pin(gnd, "G", "VSS", PinType.OUTPUT)
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# VCC is the logic high level generator
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tt.create_wire('VCC', 'VCC')
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gnd = tt.create_bel('VCC', 'VCC', z = VCC_Z)
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tt.add_bel_pin(gnd, "V", "VCC", PinType.OUTPUT)
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create_switch_matrix(tt, db, x, y)
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return (ttyp, tt)
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# Global set/reset. GW2A series has special cell for it
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def create_gsr_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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if ttyp in created_tiletypes:
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return ttyp, None
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typename = "GSR"
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tt = chip.create_tile_type(f"{typename}_{ttyp}")
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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portmap = db.grid[y][x].bels['GSR'].portmap
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tt.create_wire(portmap['GSRI'], "GSRI")
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io = tt.create_bel("GSR", "GSR", z = GSR_Z)
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tt.add_bel_pin(io, "GSRI", portmap['GSRI'], PinType.INPUT)
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create_switch_matrix(tt, db, x, y)
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return (ttyp, tt)
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# simple IO - only A and B
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def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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if ttyp in created_tiletypes:
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return ttyp, None
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typename = "IO"
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tt = chip.create_tile_type(f"{typename}_{ttyp}")
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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for i in range(2):
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name = ['IOBA', 'IOBB'][i]
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# wires
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portmap = db.grid[y][x].bels[name].portmap
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tt.create_wire(portmap['I'], "IO_I")
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tt.create_wire(portmap['O'], "IO_O")
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# bels
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io = tt.create_bel(name, "IOB", z = i)
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tt.add_bel_pin(io, "I", portmap['I'], PinType.INPUT)
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tt.add_bel_pin(io, "O", portmap['O'], PinType.OUTPUT)
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create_switch_matrix(tt, db, x, y)
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return (ttyp, tt)
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# logic: luts, dffs, alu etc
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def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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if ttyp in created_tiletypes:
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return ttyp, None
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typename = "LOGIC"
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tt = chip.create_tile_type(f"{typename}_{ttyp}")
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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lut_inputs = ['A', 'B', 'C', 'D']
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# setup LUT wires
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for i in range(8):
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for inp_name in lut_inputs:
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tt.create_wire(f"{inp_name}{i}", "LUT_INPUT")
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tt.create_wire(f"F{i}", "LUT_OUT")
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# experimental. the wire is false - it is assumed that DFF is always
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# connected to the LUT's output F{i}, but we can place primitives
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# arbitrarily and create a pass-through LUT afterwards.
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# just out of curiosity
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tt.create_wire(f"XD{i}", "FF_INPUT")
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tt.create_wire(f"Q{i}", "FF_OUT")
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# setup DFF wires
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for j in range(3):
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tt.create_wire(f"CLK{j}", "TILE_CLK")
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tt.create_wire(f"LSR{j}", "TILE_LSR")
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tt.create_wire(f"CE{j}", "TILE_CE")
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# setup MUX2 wires
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for j in range(8):
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tt.create_wire(f"OF{j}", "MUX_OUT")
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tt.create_wire(f"SEL{j}", "MUX_SEL")
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tt.create_wire("OF30", "MUX_OUT")
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# setup ALU wires
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for j in range(6):
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tt.create_wire(f"CIN{j}", "ALU_CIN")
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tt.create_wire(f"COUT{j}", "ALU_COUT")
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# create logic cells
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for i in range(8):
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# LUT
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lut = tt.create_bel(f"LUT{i}", "LUT4", z = (i * 2 + 0))
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for j, inp_name in enumerate(lut_inputs):
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tt.add_bel_pin(lut, f"I{j}", f"{inp_name}{i}", PinType.INPUT)
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tt.add_bel_pin(lut, "F", f"F{i}", PinType.OUTPUT)
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if i < 6:
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# FF data can come from LUT output, but we pretend that we can use
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# any LUT input
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tt.create_pip(f"F{i}", f"XD{i}")
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for inp_name in lut_inputs:
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tt.create_pip(f"{inp_name}{i}", f"XD{i}")
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# FF
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ff = tt.create_bel(f"DFF{i}", "DFF", z =(i * 2 + 1))
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tt.add_bel_pin(ff, "D", f"XD{i}", PinType.INPUT)
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tt.add_bel_pin(ff, "CLK", f"CLK{i // 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "Q", f"Q{i}", PinType.OUTPUT)
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tt.add_bel_pin(ff, "SET", f"LSR{i // 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "RESET", f"LSR{i // 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "PRESET", f"LSR{i // 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "CLEAR", f"LSR{i // 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "CE", f"CE{i // 2}", PinType.INPUT)
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# ALU
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ff = tt.create_bel(f"ALU{i}", "ALU", z = i + ALU0_Z)
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tt.add_bel_pin(ff, "SUM", f"F{i}", PinType.OUTPUT)
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tt.add_bel_pin(ff, "COUT", f"COUT{i}", PinType.OUTPUT)
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tt.add_bel_pin(ff, "CIN", f"CIN{i}", PinType.INPUT)
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# pinout for the ADDSUB ALU mode
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tt.add_bel_pin(ff, "I0", f"A{i}", PinType.INPUT)
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tt.add_bel_pin(ff, "I1", f"B{i}", PinType.INPUT)
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tt.add_bel_pin(ff, "I2", f"C{i}", PinType.INPUT)
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tt.add_bel_pin(ff, "I3", f"D{i}", PinType.INPUT)
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# wide luts
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for i in range(4):
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ff = tt.create_bel(f"MUX{i * 2}", "MUX2_LUT5", z = MUX20_Z + i * 4)
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tt.add_bel_pin(ff, "I0", f"F{i * 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "I1", f"F{i * 2 + 1}", PinType.INPUT)
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tt.add_bel_pin(ff, "O", f"OF{i * 2}", PinType.OUTPUT)
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tt.add_bel_pin(ff, "S0", f"SEL{i * 2}", PinType.INPUT)
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for i in range(2):
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ff = tt.create_bel(f"MUX{i * 4 + 1}", "MUX2_LUT6", z = MUX21_Z + i * 8)
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tt.add_bel_pin(ff, "I0", f"OF{i * 4 + 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "I1", f"OF{i * 4}", PinType.INPUT)
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tt.add_bel_pin(ff, "O", f"OF{i * 4 + 1}", PinType.OUTPUT)
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tt.add_bel_pin(ff, "S0", f"SEL{i * 4 + 1}", PinType.INPUT)
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ff = tt.create_bel(f"MUX3", "MUX2_LUT7", z = MUX23_Z)
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tt.add_bel_pin(ff, "I0", f"OF5", PinType.INPUT)
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tt.add_bel_pin(ff, "I1", f"OF1", PinType.INPUT)
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tt.add_bel_pin(ff, "O", f"OF3", PinType.OUTPUT)
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tt.add_bel_pin(ff, "S0", f"SEL3", PinType.INPUT)
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ff = tt.create_bel(f"MUX7", "MUX2_LUT8", z = MUX27_Z)
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tt.add_bel_pin(ff, "I0", f"OF30", PinType.INPUT)
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tt.add_bel_pin(ff, "I1", f"OF3", PinType.INPUT)
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tt.add_bel_pin(ff, "O", f"OF7", PinType.OUTPUT)
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tt.add_bel_pin(ff, "S0", f"SEL7", PinType.INPUT)
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create_switch_matrix(tt, db, x, y)
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return (ttyp, tt)
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def create_ssram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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if ttyp in created_tiletypes:
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return ttyp, None
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# SSRAM is LUT based, so it's logic-like
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ttyp, tt = create_logic_tiletype(chip, db, x, y, ttyp)
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lut_inputs = ['A', 'B', 'C', 'D']
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ff = tt.create_bel(f"RAM16SDP4", "RAM16SDP4", z = RAMW_Z)
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for i in range(4):
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tt.add_bel_pin(ff, f"DI[{i}]", f"{lut_inputs[i]}5", PinType.INPUT)
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tt.add_bel_pin(ff, f"WAD[{i}]", f"{lut_inputs[i]}4", PinType.INPUT)
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# RAD[0] is assumed to be connected to A3, A2, A1 and A0. But
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# for now we connect it only to A0, the others will be connected
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# directly during packing. RAD[1...3] - similarly.
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tt.add_bel_pin(ff, f"RAD[{i}]", f"{lut_inputs[i]}0", PinType.INPUT)
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tt.add_bel_pin(ff, f"DO[{i}]", f"F{i}", PinType.OUTPUT)
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tt.add_bel_pin(ff, f"CLK", "CLK2", PinType.INPUT)
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tt.add_bel_pin(ff, f"CE", "CE2", PinType.INPUT)
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tt.add_bel_pin(ff, f"WRE", "LSR2", PinType.INPUT)
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return (ttyp, tt)
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# PLL main tile
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_pll_inputs = {'CLKFB', 'FBDSEL0', 'FBDSEL1', 'FBDSEL2', 'FBDSEL3',
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'FBDSEL4', 'FBDSEL5', 'IDSEL0', 'IDSEL1', 'IDSEL2', 'IDSEL3',
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'IDSEL4', 'IDSEL5', 'ODSEL0', 'ODSEL1', 'ODSEL2', 'ODSEL3',
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'ODSEL4', 'ODSEL5', 'RESET', 'RESET_P', 'PSDA0', 'PSDA1',
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'PSDA2', 'PSDA3', 'DUTYDA0', 'DUTYDA1', 'DUTYDA2', 'DUTYDA3',
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'FDLY0', 'FDLY1', 'FDLY2', 'FDLY3', 'CLKIN'}
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_pll_outputs = {'CLKOUT', 'LOCK', 'CLKOUTP', 'CLKOUTD', 'CLKOUTD3'}
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def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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if ttyp in created_tiletypes:
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return ttyp, None
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typename = "PLL"
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tt = chip.create_tile_type(f"{typename}_{ttyp}")
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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# wires
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if chip.name == 'GW1NS-4':
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pll_name = 'PLLVR'
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bel_type = 'PLLVR'
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else:
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pll_name = 'RPLLA'
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bel_type = 'rPLL'
|
|
portmap = db.grid[y][x].bels[pll_name].portmap
|
|
pll = tt.create_bel("PLL", bel_type, z = PLL_Z)
|
|
# Not sure how this will affect routing - PLLs are fixed and their outputs
|
|
# will be handled by a dedicated router
|
|
#pll.flags = BEL_FLAG_GLOBAL
|
|
for pin, wire in portmap.items():
|
|
if pin in _pll_inputs:
|
|
tt.create_wire(wire, "PLL_I")
|
|
tt.add_bel_pin(pll, pin, wire, PinType.INPUT)
|
|
else:
|
|
assert pin in _pll_outputs, f"Unknown PLL pin{pin}"
|
|
tt.create_wire(wire, "PLL_O")
|
|
tt.add_bel_pin(pll, pin, wire, PinType.OUTPUT)
|
|
|
|
create_switch_matrix(tt, db, x, y)
|
|
return (ttyp, tt)
|
|
|
|
# pinouts, packages...
|
|
_tbrlre = re.compile(r"IO([TBRL])(\d+)(\w)")
|
|
def create_packages(chip: Chip, db: chipdb):
|
|
def ioloc_to_tile_bel(ioloc):
|
|
side, num, bel_idx = _tbrlre.match(ioloc).groups()
|
|
if side == 'T':
|
|
row = 0
|
|
col = int(num) - 1
|
|
elif side == 'B':
|
|
row = db.rows - 1
|
|
col = int(num) - 1
|
|
elif side == 'L':
|
|
row = int(num) - 1
|
|
col = 0
|
|
elif side == 'R':
|
|
row = int(num) - 1
|
|
col = db.cols - 1
|
|
return (f'X{col}Y{row}', f'IOB{bel_idx}')
|
|
|
|
created_pkgs = set()
|
|
for partno_spd, partdata in db.packages.items():
|
|
pkgname, variant, spd = partdata
|
|
partno = partno_spd.removesuffix(spd) # drop SPEED like 'C7/I6'
|
|
if partno in created_pkgs:
|
|
continue
|
|
created_pkgs.add(partno)
|
|
pkg = chip.create_package(partno)
|
|
for pinno, pininfo in db.pinout[variant][pkgname].items():
|
|
io_loc, cfgs = pininfo
|
|
tile, bel = ioloc_to_tile_bel(io_loc)
|
|
pad_func = ""
|
|
for cfg in cfgs:
|
|
pad_func += cfg + "/"
|
|
pad_func = pad_func.rstrip('/')
|
|
bank = int(db.pin_bank[io_loc])
|
|
pad = pkg.create_pad(pinno, tile, bel, pad_func, bank)
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(description='Make Gowin BBA')
|
|
parser.add_argument('-d', '--device', required=True)
|
|
parser.add_argument('-o', '--output', default="out.bba")
|
|
|
|
args = parser.parse_args()
|
|
|
|
device = args.device
|
|
with gzip.open(importlib.resources.files("apycula").joinpath(f"{device}.pickle"), 'rb') as f:
|
|
db = pickle.load(f)
|
|
|
|
X = db.cols;
|
|
Y = db.rows;
|
|
|
|
ch = Chip("gowin", device, X, Y)
|
|
|
|
# Init constant ids
|
|
ch.strs.read_constids(path.join(path.dirname(__file__), "constids.inc"))
|
|
|
|
# packages from parntnumbers
|
|
create_packages(ch, db)
|
|
|
|
# The manufacturer distinguishes by externally identical tiles, so keep
|
|
# these differences (in case it turns out later that there is a slightly
|
|
# different routing or something like that).
|
|
logic_tiletypes = {12, 13, 14, 15, 16}
|
|
io_tiletypes = {52, 53, 54, 55, 58, 59, 64, 65, 66}
|
|
ssram_tiletypes = {17, 18, 19}
|
|
gsr_tiletypes = {1}
|
|
pll_tiletypes = {86, 87, 42, 45}
|
|
# Setup tile grid
|
|
for x in range(X):
|
|
for y in range(Y):
|
|
ttyp = db.grid[y][x].ttyp
|
|
if (x == 0 or x == X - 1) and (y == 0 or y == Y - 1):
|
|
assert ttyp not in created_tiletypes, "Duplication of corner types"
|
|
ttyp, _ = create_corner_tiletype(ch, db, x, y, ttyp)
|
|
created_tiletypes.add(ttyp)
|
|
ch.set_tile_type(x, y, f"CORNER_{ttyp}")
|
|
continue
|
|
if ttyp in gsr_tiletypes:
|
|
ttyp, _ = create_gsr_tiletype(ch, db, x, y, ttyp)
|
|
created_tiletypes.add(ttyp)
|
|
ch.set_tile_type(x, y, f"GSR_{ttyp}")
|
|
elif ttyp in logic_tiletypes:
|
|
ttyp, _ = create_logic_tiletype(ch, db, x, y, ttyp)
|
|
created_tiletypes.add(ttyp)
|
|
ch.set_tile_type(x, y, f"LOGIC_{ttyp}")
|
|
elif ttyp in ssram_tiletypes:
|
|
ttyp, _ = create_ssram_tiletype(ch, db, x, y, ttyp)
|
|
created_tiletypes.add(ttyp)
|
|
ch.set_tile_type(x, y, f"LOGIC_{ttyp}")
|
|
elif ttyp in io_tiletypes:
|
|
ttyp, _ = create_io_tiletype(ch, db, x, y, ttyp)
|
|
created_tiletypes.add(ttyp)
|
|
ch.set_tile_type(x, y, f"IO_{ttyp}")
|
|
elif ttyp in pll_tiletypes:
|
|
ttyp, _ = create_pll_tiletype(ch, db, x, y, ttyp)
|
|
created_tiletypes.add(ttyp)
|
|
ch.set_tile_type(x, y, f"PLL_{ttyp}")
|
|
else:
|
|
ttyp, _ = create_null_tiletype(ch, db, x, y, ttyp)
|
|
created_tiletypes.add(ttyp)
|
|
ch.set_tile_type(x, y, f"NULL_{ttyp}")
|
|
|
|
# Create nodes between tiles
|
|
create_nodes(ch, db)
|
|
ch.write_bba(args.output)
|
|
if __name__ == '__main__':
|
|
main()
|