1112 lines
49 KiB
C++
1112 lines
49 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 David Shah <david@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <algorithm>
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#include <boost/optional.hpp>
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#include <iterator>
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#include <unordered_set>
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#include "cells.h"
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#include "chain_utils.h"
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#include "design_utils.h"
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#include "log.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
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{
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return cell->type == ctx->id("$nextpnr_ibuf") || cell->type == ctx->id("$nextpnr_obuf") ||
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cell->type == ctx->id("$nextpnr_iobuf");
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}
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class Ecp5Packer
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{
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public:
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Ecp5Packer(Context *ctx) : ctx(ctx){};
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private:
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// Process the contents of packed_cells and new_cells
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void flush_cells()
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{
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for (auto pcell : packed_cells) {
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ctx->cells.erase(pcell);
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}
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for (auto &ncell : new_cells) {
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ctx->cells[ncell->name] = std::move(ncell);
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}
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packed_cells.clear();
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new_cells.clear();
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}
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// Find FFs associated with LUTs, or LUT expansion muxes
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void find_lutff_pairs()
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{
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log_info("Finding LUTFF pairs...\n");
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for (auto cell : sorted(ctx->cells)) {
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CellInfo *ci = cell.second;
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if (is_lut(ctx, ci) || is_pfumx(ctx, ci) || is_l6mux(ctx, ci)) {
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NetInfo *znet = ci->ports.at(ctx->id("Z")).net;
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if (znet != nullptr) {
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CellInfo *ff = net_only_drives(ctx, znet, is_ff, ctx->id("DI"), false);
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if (ff != nullptr) {
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lutffPairs[ci->name] = ff->name;
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fflutPairs[ff->name] = ci->name;
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}
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}
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}
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}
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}
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const NetInfo *net_or_nullptr(CellInfo *cell, IdString port)
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{
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auto fnd = cell->ports.find(port);
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if (fnd == cell->ports.end())
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return nullptr;
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else
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return fnd->second.net;
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}
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// Return whether two FFs can be packed together in the same slice
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bool can_pack_ffs(CellInfo *ff0, CellInfo *ff1)
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{
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if (str_or_default(ff0->params, ctx->id("GSR"), "DISABLED") !=
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str_or_default(ff1->params, ctx->id("GSR"), "DISABLED"))
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return false;
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if (str_or_default(ff0->params, ctx->id("SRMODE"), "LSR_OVER_CE") !=
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str_or_default(ff1->params, ctx->id("SRMODE"), "LSR_OVER_CE"))
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return false;
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if (str_or_default(ff0->params, ctx->id("CEMUX"), "1") != str_or_default(ff1->params, ctx->id("CEMUX"), "1"))
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return false;
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if (str_or_default(ff0->params, ctx->id("LSRMUX"), "LSR") !=
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str_or_default(ff1->params, ctx->id("LSRMUX"), "LSR"))
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return false;
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if (str_or_default(ff0->params, ctx->id("CLKMUX"), "CLK") !=
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str_or_default(ff1->params, ctx->id("CLKMUX"), "CLK"))
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return false;
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if (net_or_nullptr(ff0, ctx->id("CLK")) != net_or_nullptr(ff1, ctx->id("CLK")))
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return false;
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if (net_or_nullptr(ff0, ctx->id("CE")) != net_or_nullptr(ff1, ctx->id("CE")))
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return false;
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if (net_or_nullptr(ff0, ctx->id("LSR")) != net_or_nullptr(ff1, ctx->id("LSR")))
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return false;
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return true;
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}
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// Return whether or not an FF can be added to a tile (pairing checks must also be done using the fn above)
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bool can_add_ff_to_tile(const std::vector<CellInfo *> &tile_ffs, CellInfo *ff0)
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{
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for (const auto &existing : tile_ffs) {
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if (net_or_nullptr(existing, ctx->id("CLK")) != net_or_nullptr(ff0, ctx->id("CLK")))
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return false;
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if (net_or_nullptr(existing, ctx->id("LSR")) != net_or_nullptr(ff0, ctx->id("LSR")))
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return false;
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if (str_or_default(existing->params, ctx->id("CLKMUX"), "CLK") !=
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str_or_default(ff0->params, ctx->id("CLKMUX"), "CLK"))
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return false;
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if (str_or_default(existing->params, ctx->id("LSRMUX"), "LSR") !=
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str_or_default(ff0->params, ctx->id("LSRMUX"), "LSR"))
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return false;
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if (str_or_default(existing->params, ctx->id("SRMODE"), "LSR_OVER_CE") !=
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str_or_default(ff0->params, ctx->id("SRMODE"), "LSR_OVER_CE"))
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return false;
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}
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return true;
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}
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// Return true if a FF can be added to a DPRAM slice
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bool can_pack_ff_dram(CellInfo *dpram, CellInfo *ff)
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{
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std::string wckmux = str_or_default(dpram->params, ctx->id("WCKMUX"), "WCK");
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std::string clkmux = str_or_default(ff->params, ctx->id("CLKMUX"), "CLK");
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if (wckmux != clkmux && !(wckmux == "WCK" && clkmux == "CLK"))
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return false;
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std::string wremux = str_or_default(dpram->params, ctx->id("WREMUX"), "WRE");
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std::string lsrmux = str_or_default(ff->params, ctx->id("LSRMUX"), "LSR");
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if (wremux != lsrmux && !(wremux == "WRE" && lsrmux == "LSR"))
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return false;
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return true;
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}
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// Return true if two LUTs can be paired considering FF compatibility
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bool can_pack_lutff(IdString lut0, IdString lut1)
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{
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auto ff0 = lutffPairs.find(lut0), ff1 = lutffPairs.find(lut1);
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if (ff0 != lutffPairs.end() && ff1 != lutffPairs.end()) {
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return can_pack_ffs(ctx->cells.at(ff0->second).get(), ctx->cells.at(ff1->second).get());
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} else {
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return true;
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}
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}
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// Find "closely connected" LUTs and pair them together
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void pair_luts()
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{
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log_info("Finding LUT-LUT pairs...\n");
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std::unordered_set<IdString> procdLuts;
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for (auto cell : sorted(ctx->cells)) {
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CellInfo *ci = cell.second;
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if (is_lut(ctx, ci) && procdLuts.find(cell.first) == procdLuts.end()) {
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NetInfo *znet = ci->ports.at(ctx->id("Z")).net;
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if (znet != nullptr) {
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for (auto user : znet->users) {
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if (is_lut(ctx, user.cell) && user.cell != ci &&
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procdLuts.find(user.cell->name) == procdLuts.end()) {
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if (can_pack_lutff(ci->name, user.cell->name)) {
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procdLuts.insert(ci->name);
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procdLuts.insert(user.cell->name);
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lutPairs[ci->name] = user.cell->name;
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goto paired;
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}
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}
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}
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if (false) {
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paired:
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continue;
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}
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}
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if (lutffPairs.find(ci->name) != lutffPairs.end()) {
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NetInfo *qnet = ctx->cells.at(lutffPairs[ci->name])->ports.at(ctx->id("Q")).net;
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if (qnet != nullptr) {
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for (auto user : qnet->users) {
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if (is_lut(ctx, user.cell) && user.cell != ci &&
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procdLuts.find(user.cell->name) == procdLuts.end()) {
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if (can_pack_lutff(ci->name, user.cell->name)) {
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procdLuts.insert(ci->name);
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procdLuts.insert(user.cell->name);
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lutPairs[ci->name] = user.cell->name;
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goto paired_ff;
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}
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}
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}
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if (false) {
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paired_ff:
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continue;
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}
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}
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}
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for (const char *inp : {"A", "B", "C", "D"}) {
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NetInfo *innet = ci->ports.at(ctx->id(inp)).net;
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if (innet != nullptr && innet->driver.cell != nullptr) {
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CellInfo *drv = innet->driver.cell;
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if (is_lut(ctx, drv) && drv != ci && innet->driver.port == ctx->id("Z")) {
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if (procdLuts.find(drv->name) == procdLuts.end()) {
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if (can_pack_lutff(ci->name, drv->name)) {
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procdLuts.insert(ci->name);
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procdLuts.insert(drv->name);
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lutPairs[ci->name] = drv->name;
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goto paired_inlut;
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}
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}
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} else if (is_ff(ctx, drv) && innet->driver.port == ctx->id("Q")) {
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auto fflut = fflutPairs.find(drv->name);
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if (fflut != fflutPairs.end() && fflut->second != ci->name &&
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procdLuts.find(fflut->second) == procdLuts.end()) {
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if (can_pack_lutff(ci->name, fflut->second)) {
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procdLuts.insert(ci->name);
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procdLuts.insert(fflut->second);
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lutPairs[ci->name] = fflut->second;
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goto paired_inlut;
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}
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}
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}
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}
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}
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if (false) {
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paired_inlut:
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continue;
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}
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}
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}
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}
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// Simple "packer" to remove nextpnr IOBUFs, this assumes IOBUFs are manually instantiated
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void pack_io()
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{
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log_info("Packing IOs..\n");
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for (auto cell : sorted(ctx->cells)) {
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CellInfo *ci = cell.second;
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if (is_nextpnr_iob(ctx, ci)) {
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CellInfo *trio = nullptr;
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if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
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trio = net_only_drives(ctx, ci->ports.at(ctx->id("O")).net, is_trellis_io, ctx->id("B"), true, ci);
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} else if (ci->type == ctx->id("$nextpnr_obuf")) {
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trio = net_only_drives(ctx, ci->ports.at(ctx->id("I")).net, is_trellis_io, ctx->id("B"), true, ci);
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}
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if (trio != nullptr) {
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// Trivial case, TRELLIS_IO used. Just destroy the net and the
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// iobuf
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log_info("%s feeds TRELLIS_IO %s, removing %s %s.\n", ci->name.c_str(ctx), trio->name.c_str(ctx),
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ci->type.c_str(ctx), ci->name.c_str(ctx));
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NetInfo *net = trio->ports.at(ctx->id("B")).net;
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if (net != nullptr) {
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ctx->nets.erase(net->name);
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trio->ports.at(ctx->id("B")).net = nullptr;
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}
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if (ci->type == ctx->id("$nextpnr_iobuf")) {
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NetInfo *net2 = ci->ports.at(ctx->id("I")).net;
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if (net2 != nullptr) {
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ctx->nets.erase(net2->name);
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}
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}
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} else {
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log_error("TRELLIS_IO required on all top level IOs...\n");
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}
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packed_cells.insert(ci->name);
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std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(trio->attrs, trio->attrs.begin()));
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auto loc_attr = trio->attrs.find(ctx->id("LOC"));
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if (loc_attr != trio->attrs.end()) {
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std::string pin = loc_attr->second;
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BelId pinBel = ctx->getPackagePinBel(pin);
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if (pinBel == BelId()) {
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log_error("IO pin '%s' constrained to pin '%s', which does not exist for package '%s'.\n",
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trio->name.c_str(ctx), pin.c_str(), ctx->args.package.c_str());
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} else {
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log_info("pin '%s' constrained to Bel '%s'.\n", trio->name.c_str(ctx),
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ctx->getBelName(pinBel).c_str(ctx));
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}
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trio->attrs[ctx->id("BEL")] = ctx->getBelName(pinBel).str(ctx);
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}
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}
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}
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flush_cells();
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}
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// Pass to pack LUT5s into a newly created slice
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void pack_lut5s()
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{
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log_info("Packing LUT5s...\n");
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for (auto cell : sorted(ctx->cells)) {
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CellInfo *ci = cell.second;
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if (is_pfumx(ctx, ci)) {
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std::unique_ptr<CellInfo> packed =
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create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE");
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NetInfo *f0 = ci->ports.at(ctx->id("BLUT")).net;
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if (f0 == nullptr)
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log_error("PFUMX '%s' has disconnected port 'BLUT'\n", ci->name.c_str(ctx));
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NetInfo *f1 = ci->ports.at(ctx->id("ALUT")).net;
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if (f1 == nullptr)
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log_error("PFUMX '%s' has disconnected port 'ALUT'\n", ci->name.c_str(ctx));
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CellInfo *lut0 = net_driven_by(ctx, f0, is_lut, ctx->id("Z"));
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CellInfo *lut1 = net_driven_by(ctx, f1, is_lut, ctx->id("Z"));
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if (lut0 == nullptr)
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log_error("PFUMX '%s' has BLUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
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if (lut1 == nullptr)
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log_error("PFUMX '%s' has ALUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
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replace_port(lut0, ctx->id("A"), packed.get(), ctx->id("A0"));
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replace_port(lut0, ctx->id("B"), packed.get(), ctx->id("B0"));
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replace_port(lut0, ctx->id("C"), packed.get(), ctx->id("C0"));
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replace_port(lut0, ctx->id("D"), packed.get(), ctx->id("D0"));
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replace_port(lut1, ctx->id("A"), packed.get(), ctx->id("A1"));
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replace_port(lut1, ctx->id("B"), packed.get(), ctx->id("B1"));
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replace_port(lut1, ctx->id("C"), packed.get(), ctx->id("C1"));
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replace_port(lut1, ctx->id("D"), packed.get(), ctx->id("D1"));
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replace_port(ci, ctx->id("C0"), packed.get(), ctx->id("M0"));
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replace_port(ci, ctx->id("Z"), packed.get(), ctx->id("OFX0"));
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packed->params[ctx->id("LUT0_INITVAL")] = str_or_default(lut0->params, ctx->id("INIT"), "0");
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packed->params[ctx->id("LUT1_INITVAL")] = str_or_default(lut1->params, ctx->id("INIT"), "0");
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ctx->nets.erase(f0->name);
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ctx->nets.erase(f1->name);
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sliceUsage[packed->name].lut0_used = true;
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sliceUsage[packed->name].lut1_used = true;
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sliceUsage[packed->name].mux5_used = true;
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if (lutffPairs.find(ci->name) != lutffPairs.end()) {
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CellInfo *ff = ctx->cells.at(lutffPairs[ci->name]).get();
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ff_to_slice(ctx, ff, packed.get(), 0, true);
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packed_cells.insert(ff->name);
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sliceUsage[packed->name].ff0_used = true;
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lutffPairs.erase(ci->name);
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fflutPairs.erase(ff->name);
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}
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new_cells.push_back(std::move(packed));
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packed_cells.insert(lut0->name);
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packed_cells.insert(lut1->name);
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packed_cells.insert(ci->name);
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}
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}
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flush_cells();
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}
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// Create a feed in to the carry chain
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CellInfo *make_carry_feed_in(NetInfo *carry, PortRef chain_in)
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{
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std::unique_ptr<CellInfo> feedin = create_ecp5_cell(ctx, ctx->id("CCU2C"));
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feedin->params[ctx->id("INIT0")] = "10"; // LUT4 = 0; LUT2 = A
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feedin->params[ctx->id("INIT1")] = "65535";
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feedin->params[ctx->id("INJECT1_0")] = "NO";
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feedin->params[ctx->id("INJECT1_1")] = "YES";
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carry->users.erase(std::remove_if(carry->users.begin(), carry->users.end(),
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[chain_in](const PortRef &user) {
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return user.port == chain_in.port && user.cell == chain_in.cell;
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}),
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carry->users.end());
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connect_port(ctx, carry, feedin.get(), id_A0);
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std::unique_ptr<NetInfo> new_carry(new NetInfo());
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new_carry->name = ctx->id(feedin->name.str(ctx) + "$COUT");
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connect_port(ctx, new_carry.get(), feedin.get(), ctx->id("COUT"));
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chain_in.cell->ports[chain_in.port].net = nullptr;
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connect_port(ctx, new_carry.get(), chain_in.cell, chain_in.port);
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CellInfo *feedin_ptr = feedin.get();
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IdString feedin_name = feedin->name;
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ctx->cells[feedin_name] = std::move(feedin);
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IdString new_carry_name = new_carry->name;
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ctx->nets[new_carry_name] = std::move(new_carry);
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return feedin_ptr;
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}
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// Create a feed out and loop through from the carry chain
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CellInfo *make_carry_feed_out(NetInfo *carry, boost::optional<PortRef> chain_next = boost::optional<PortRef>())
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{
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std::unique_ptr<CellInfo> feedout = create_ecp5_cell(ctx, ctx->id("CCU2C"));
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feedout->params[ctx->id("INIT0")] = "0";
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feedout->params[ctx->id("INIT1")] = "10"; // LUT4 = 0; LUT2 = A
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feedout->params[ctx->id("INJECT1_0")] = "NO";
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feedout->params[ctx->id("INJECT1_1")] = "NO";
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PortRef carry_drv = carry->driver;
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carry->driver.cell = nullptr;
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connect_port(ctx, carry, feedout.get(), ctx->id("S0"));
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std::unique_ptr<NetInfo> new_cin(new NetInfo());
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new_cin->name = ctx->id(feedout->name.str(ctx) + "$CIN");
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new_cin->driver = carry_drv;
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carry_drv.cell->ports.at(carry_drv.port).net = new_cin.get();
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connect_port(ctx, new_cin.get(), feedout.get(), ctx->id("CIN"));
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if (chain_next) {
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// Loop back into LUT4_1 for feedthrough
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connect_port(ctx, carry, feedout.get(), id_A1);
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|
|
|
carry->users.erase(std::remove_if(carry->users.begin(), carry->users.end(),
|
|
[chain_next](const PortRef &user) {
|
|
return user.port == chain_next->port && user.cell == chain_next->cell;
|
|
}),
|
|
carry->users.end());
|
|
|
|
std::unique_ptr<NetInfo> new_cout(new NetInfo());
|
|
new_cout->name = ctx->id(feedout->name.str(ctx) + "$COUT");
|
|
connect_port(ctx, new_cout.get(), feedout.get(), ctx->id("COUT"));
|
|
|
|
chain_next->cell->ports[chain_next->port].net = nullptr;
|
|
connect_port(ctx, new_cout.get(), chain_next->cell, chain_next->port);
|
|
|
|
IdString new_cout_name = new_cout->name;
|
|
ctx->nets[new_cout_name] = std::move(new_cout);
|
|
}
|
|
|
|
CellInfo *feedout_ptr = feedout.get();
|
|
IdString feedout_name = feedout->name;
|
|
ctx->cells[feedout_name] = std::move(feedout);
|
|
|
|
IdString new_cin_name = new_cin->name;
|
|
ctx->nets[new_cin_name] = std::move(new_cin);
|
|
|
|
return feedout_ptr;
|
|
}
|
|
|
|
// Split a carry chain into multiple legal chains
|
|
std::vector<CellChain> split_carry_chain(CellChain &carryc)
|
|
{
|
|
bool start_of_chain = true;
|
|
std::vector<CellChain> chains;
|
|
const int max_length = (ctx->chip_info->width - 4) * 4 - 2;
|
|
auto curr_cell = carryc.cells.begin();
|
|
while (curr_cell != carryc.cells.end()) {
|
|
CellInfo *cell = *curr_cell;
|
|
if (start_of_chain) {
|
|
chains.emplace_back();
|
|
start_of_chain = false;
|
|
if (cell->ports.at(ctx->id("CIN")).net) {
|
|
// CIN is not constant and not part of a chain. Must feed in from fabric
|
|
PortRef inport;
|
|
inport.cell = cell;
|
|
inport.port = ctx->id("CIN");
|
|
CellInfo *feedin = make_carry_feed_in(cell->ports.at(ctx->id("CIN")).net, inport);
|
|
chains.back().cells.push_back(feedin);
|
|
}
|
|
}
|
|
chains.back().cells.push_back(cell);
|
|
bool split_chain = int(chains.back().cells.size()) > max_length;
|
|
if (split_chain) {
|
|
CellInfo *passout = make_carry_feed_out(cell->ports.at(ctx->id("COUT")).net);
|
|
chains.back().cells.back() = passout;
|
|
start_of_chain = true;
|
|
} else {
|
|
NetInfo *carry_net = cell->ports.at(ctx->id("COUT")).net;
|
|
bool at_end = (curr_cell == carryc.cells.end() - 1);
|
|
if (carry_net != nullptr && (carry_net->users.size() > 1 || at_end)) {
|
|
boost::optional<PortRef> nextport;
|
|
if (!at_end) {
|
|
auto next_cell = *(curr_cell + 1);
|
|
PortRef nextpr;
|
|
nextpr.cell = next_cell;
|
|
nextpr.port = ctx->id("CIN");
|
|
nextport = nextpr;
|
|
}
|
|
CellInfo *passout = make_carry_feed_out(cell->ports.at(ctx->id("COUT")).net, nextport);
|
|
chains.back().cells.push_back(passout);
|
|
}
|
|
++curr_cell;
|
|
}
|
|
}
|
|
return chains;
|
|
}
|
|
|
|
// Pack carries and set up appropriate relative constraints
|
|
void pack_carries()
|
|
{
|
|
log_info("Packing carries...\n");
|
|
// Find all chains (including single carry cells)
|
|
auto carry_chains = find_chains(
|
|
ctx, [](const Context *ctx, const CellInfo *cell) { return is_carry(ctx, cell); },
|
|
[](const Context *ctx, const CellInfo *cell) {
|
|
return net_driven_by(ctx, cell->ports.at(ctx->id("CIN")).net, is_carry, ctx->id("COUT"));
|
|
},
|
|
[](const Context *ctx, const CellInfo *cell) {
|
|
return net_only_drives(ctx, cell->ports.at(ctx->id("COUT")).net, is_carry, ctx->id("CIN"), false);
|
|
},
|
|
1);
|
|
std::vector<CellChain> all_chains;
|
|
|
|
// Chain splitting
|
|
for (auto &base_chain : carry_chains) {
|
|
if (ctx->verbose) {
|
|
log_info("Found carry chain: \n");
|
|
for (auto entry : base_chain.cells)
|
|
log_info(" %s\n", entry->name.c_str(ctx));
|
|
log_info("\n");
|
|
}
|
|
std::vector<CellChain> split_chains = split_carry_chain(base_chain);
|
|
for (auto &chain : split_chains) {
|
|
all_chains.push_back(chain);
|
|
}
|
|
}
|
|
|
|
std::vector<std::vector<CellInfo *>> packed_chains;
|
|
|
|
// Chain packing
|
|
std::vector<std::tuple<CellInfo *, CellInfo *, int>> ff_packing;
|
|
for (auto &chain : all_chains) {
|
|
int cell_count = 0;
|
|
std::vector<CellInfo *> tile_ffs;
|
|
std::vector<CellInfo *> packed_chain;
|
|
for (auto &cell : chain.cells) {
|
|
if (cell_count % 4 == 0)
|
|
tile_ffs.clear();
|
|
std::unique_ptr<CellInfo> slice =
|
|
create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), cell->name.str(ctx) + "$CCU2_SLICE");
|
|
|
|
ccu2c_to_slice(ctx, cell, slice.get());
|
|
|
|
CellInfo *ff0 = nullptr;
|
|
NetInfo *f0net = slice->ports.at(ctx->id("F0")).net;
|
|
if (f0net != nullptr) {
|
|
ff0 = net_only_drives(ctx, f0net, is_ff, ctx->id("DI"), false);
|
|
if (ff0 != nullptr && can_add_ff_to_tile(tile_ffs, ff0)) {
|
|
ff_packing.push_back(std::make_tuple(ff0, slice.get(), 0));
|
|
tile_ffs.push_back(ff0);
|
|
packed_cells.insert(ff0->name);
|
|
}
|
|
}
|
|
|
|
CellInfo *ff1 = nullptr;
|
|
NetInfo *f1net = slice->ports.at(ctx->id("F1")).net;
|
|
if (f1net != nullptr) {
|
|
ff1 = net_only_drives(ctx, f1net, is_ff, ctx->id("DI"), false);
|
|
if (ff1 != nullptr && (ff0 == nullptr || can_pack_ffs(ff0, ff1)) &&
|
|
can_add_ff_to_tile(tile_ffs, ff1)) {
|
|
ff_packing.push_back(std::make_tuple(ff1, slice.get(), 1));
|
|
tile_ffs.push_back(ff1);
|
|
packed_cells.insert(ff1->name);
|
|
}
|
|
}
|
|
packed_chain.push_back(slice.get());
|
|
new_cells.push_back(std::move(slice));
|
|
packed_cells.insert(cell->name);
|
|
cell_count++;
|
|
}
|
|
packed_chains.push_back(packed_chain);
|
|
}
|
|
|
|
for (auto ff : ff_packing)
|
|
ff_to_slice(ctx, std::get<0>(ff), std::get<1>(ff), std::get<2>(ff), true);
|
|
|
|
// Relative chain placement
|
|
for (auto &chain : packed_chains) {
|
|
chain.at(0)->constr_abs_z = true;
|
|
chain.at(0)->constr_z = 0;
|
|
for (int i = 1; i < int(chain.size()); i++) {
|
|
chain.at(i)->constr_x = (i / 4);
|
|
chain.at(i)->constr_y = 0;
|
|
chain.at(i)->constr_z = i % 4;
|
|
chain.at(i)->constr_abs_z = true;
|
|
chain.at(i)->constr_parent = chain.at(0);
|
|
chain.at(0)->constr_children.push_back(chain.at(i));
|
|
}
|
|
}
|
|
|
|
flush_cells();
|
|
}
|
|
|
|
// Pack distributed RAM
|
|
void pack_dram()
|
|
{
|
|
for (auto cell : sorted(ctx->cells)) {
|
|
CellInfo *ci = cell.second;
|
|
if (is_dpram(ctx, ci)) {
|
|
|
|
// Create RAMW slice
|
|
std::unique_ptr<CellInfo> ramw_slice =
|
|
create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$RAMW_SLICE");
|
|
dram_to_ramw(ctx, ci, ramw_slice.get());
|
|
|
|
// Create actual RAM slices
|
|
std::unique_ptr<CellInfo> ram0_slice =
|
|
create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$DPRAM0_SLICE");
|
|
dram_to_ram_slice(ctx, ci, ram0_slice.get(), ramw_slice.get(), 0);
|
|
|
|
std::unique_ptr<CellInfo> ram1_slice =
|
|
create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$DPRAM1_SLICE");
|
|
dram_to_ram_slice(ctx, ci, ram1_slice.get(), ramw_slice.get(), 1);
|
|
|
|
// Disconnect ports of original cell after packing
|
|
disconnect_port(ctx, ci, id_WCK);
|
|
disconnect_port(ctx, ci, id_WRE);
|
|
|
|
disconnect_port(ctx, ci, ctx->id("RAD[0]"));
|
|
disconnect_port(ctx, ci, ctx->id("RAD[1]"));
|
|
disconnect_port(ctx, ci, ctx->id("RAD[2]"));
|
|
disconnect_port(ctx, ci, ctx->id("RAD[3]"));
|
|
|
|
// Attempt to pack FFs into RAM slices
|
|
std::vector<std::tuple<CellInfo *, CellInfo *, int>> ff_packing;
|
|
std::vector<CellInfo *> tile_ffs;
|
|
for (auto slice : {ram0_slice.get(), ram1_slice.get()}) {
|
|
CellInfo *ff0 = nullptr;
|
|
NetInfo *f0net = slice->ports.at(ctx->id("F0")).net;
|
|
if (f0net != nullptr) {
|
|
ff0 = net_only_drives(ctx, f0net, is_ff, ctx->id("DI"), false);
|
|
if (ff0 != nullptr && can_add_ff_to_tile(tile_ffs, ff0)) {
|
|
if (can_pack_ff_dram(slice, ff0)) {
|
|
ff_packing.push_back(std::make_tuple(ff0, slice, 0));
|
|
tile_ffs.push_back(ff0);
|
|
packed_cells.insert(ff0->name);
|
|
}
|
|
}
|
|
}
|
|
|
|
CellInfo *ff1 = nullptr;
|
|
NetInfo *f1net = slice->ports.at(ctx->id("F1")).net;
|
|
if (f1net != nullptr) {
|
|
ff1 = net_only_drives(ctx, f1net, is_ff, ctx->id("DI"), false);
|
|
if (ff1 != nullptr && (ff0 == nullptr || can_pack_ffs(ff0, ff1)) &&
|
|
can_add_ff_to_tile(tile_ffs, ff1)) {
|
|
if (can_pack_ff_dram(slice, ff1)) {
|
|
ff_packing.push_back(std::make_tuple(ff1, slice, 1));
|
|
tile_ffs.push_back(ff1);
|
|
packed_cells.insert(ff1->name);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
for (auto ff : ff_packing)
|
|
ff_to_slice(ctx, std::get<0>(ff), std::get<1>(ff), std::get<2>(ff), true);
|
|
|
|
// Setup placement constraints
|
|
ram0_slice->constr_abs_z = true;
|
|
ram0_slice->constr_z = 0;
|
|
|
|
ram1_slice->constr_parent = ram0_slice.get();
|
|
ram1_slice->constr_abs_z = true;
|
|
ram1_slice->constr_x = 0;
|
|
ram1_slice->constr_y = 0;
|
|
ram1_slice->constr_z = 1;
|
|
ram0_slice->constr_children.push_back(ram1_slice.get());
|
|
|
|
ramw_slice->constr_parent = ram0_slice.get();
|
|
ramw_slice->constr_abs_z = true;
|
|
ramw_slice->constr_x = 0;
|
|
ramw_slice->constr_y = 0;
|
|
ramw_slice->constr_z = 2;
|
|
ram0_slice->constr_children.push_back(ramw_slice.get());
|
|
|
|
new_cells.push_back(std::move(ram0_slice));
|
|
new_cells.push_back(std::move(ram1_slice));
|
|
new_cells.push_back(std::move(ramw_slice));
|
|
packed_cells.insert(ci->name);
|
|
}
|
|
}
|
|
flush_cells();
|
|
}
|
|
|
|
// Pack LUTs that have been paired together
|
|
void pack_lut_pairs()
|
|
{
|
|
log_info("Packing paired LUTs into a SLICE...\n");
|
|
for (auto pair : lutPairs) {
|
|
CellInfo *lut0 = ctx->cells.at(pair.first).get();
|
|
CellInfo *lut1 = ctx->cells.at(pair.second).get();
|
|
std::unique_ptr<CellInfo> slice =
|
|
create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), lut0->name.str(ctx) + "_SLICE");
|
|
|
|
lut_to_slice(ctx, lut0, slice.get(), 0);
|
|
lut_to_slice(ctx, lut1, slice.get(), 1);
|
|
|
|
auto ff0 = lutffPairs.find(lut0->name);
|
|
|
|
if (ff0 != lutffPairs.end()) {
|
|
ff_to_slice(ctx, ctx->cells.at(ff0->second).get(), slice.get(), 0, true);
|
|
packed_cells.insert(ff0->second);
|
|
fflutPairs.erase(ff0->second);
|
|
lutffPairs.erase(lut0->name);
|
|
}
|
|
|
|
auto ff1 = lutffPairs.find(lut1->name);
|
|
|
|
if (ff1 != lutffPairs.end()) {
|
|
ff_to_slice(ctx, ctx->cells.at(ff1->second).get(), slice.get(), 1, true);
|
|
packed_cells.insert(ff1->second);
|
|
fflutPairs.erase(ff1->second);
|
|
lutffPairs.erase(lut1->name);
|
|
}
|
|
|
|
new_cells.push_back(std::move(slice));
|
|
packed_cells.insert(lut0->name);
|
|
packed_cells.insert(lut1->name);
|
|
}
|
|
flush_cells();
|
|
}
|
|
|
|
// Pack single LUTs that weren't paired into their own slice,
|
|
// with an optional FF also
|
|
void pack_remaining_luts()
|
|
{
|
|
log_info("Packing unpaired LUTs into a SLICE...\n");
|
|
for (auto cell : sorted(ctx->cells)) {
|
|
CellInfo *ci = cell.second;
|
|
if (is_lut(ctx, ci)) {
|
|
std::unique_ptr<CellInfo> slice =
|
|
create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE");
|
|
lut_to_slice(ctx, ci, slice.get(), 0);
|
|
auto ff = lutffPairs.find(ci->name);
|
|
|
|
if (ff != lutffPairs.end()) {
|
|
ff_to_slice(ctx, ctx->cells.at(ff->second).get(), slice.get(), 0, true);
|
|
packed_cells.insert(ff->second);
|
|
fflutPairs.erase(ff->second);
|
|
lutffPairs.erase(ci->name);
|
|
}
|
|
|
|
new_cells.push_back(std::move(slice));
|
|
packed_cells.insert(ci->name);
|
|
}
|
|
}
|
|
flush_cells();
|
|
}
|
|
|
|
// Pack flipflops that weren't paired with a LUT
|
|
void pack_remaining_ffs()
|
|
{
|
|
log_info("Packing unpaired FFs into a SLICE...\n");
|
|
for (auto cell : sorted(ctx->cells)) {
|
|
CellInfo *ci = cell.second;
|
|
if (is_ff(ctx, ci)) {
|
|
std::unique_ptr<CellInfo> slice =
|
|
create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE");
|
|
ff_to_slice(ctx, ci, slice.get(), 0, false);
|
|
new_cells.push_back(std::move(slice));
|
|
packed_cells.insert(ci->name);
|
|
}
|
|
}
|
|
flush_cells();
|
|
}
|
|
|
|
int make_init_with_const_input(int init, int input, bool value)
|
|
{
|
|
int new_init = 0;
|
|
for (int i = 0; i < 16; i++) {
|
|
if (((i >> input) & 0x1) != value) {
|
|
int other_i = (i & (~(1 << input))) | (value << input);
|
|
if ((init >> other_i) & 0x1)
|
|
new_init |= (1 << i);
|
|
} else {
|
|
if ((init >> i) & 0x1)
|
|
new_init |= (1 << i);
|
|
}
|
|
}
|
|
return new_init;
|
|
}
|
|
|
|
void set_lut_input_constant(CellInfo *cell, IdString input, bool value)
|
|
{
|
|
int index = std::string("ABCD").find(input.str(ctx));
|
|
int init = int_or_default(cell->params, ctx->id("INIT"));
|
|
int new_init = make_init_with_const_input(init, index, value);
|
|
cell->params[ctx->id("INIT")] = std::to_string(new_init);
|
|
cell->ports.at(input).net = nullptr;
|
|
}
|
|
|
|
void set_ccu2c_input_constant(CellInfo *cell, IdString input, bool value)
|
|
{
|
|
std::string input_str = input.str(ctx);
|
|
int lut = std::stoi(input_str.substr(1));
|
|
int index = std::string("ABCD").find(input_str[0]);
|
|
int init = int_or_default(cell->params, ctx->id("INIT" + std::to_string(lut)));
|
|
int new_init = make_init_with_const_input(init, index, value);
|
|
cell->params[ctx->id("INIT" + std::to_string(lut))] = std::to_string(new_init);
|
|
cell->ports.at(input).net = nullptr;
|
|
}
|
|
|
|
bool is_ccu2c_port_high(CellInfo *cell, IdString input)
|
|
{
|
|
if (!cell->ports.count(input))
|
|
return true; // disconnected port is high
|
|
if (cell->ports.at(input).net == nullptr || cell->ports.at(input).net->name == ctx->id("$PACKER_VCC_NET"))
|
|
return true; // disconnected or tied-high port
|
|
if (cell->ports.at(input).net->driver.cell != nullptr &&
|
|
cell->ports.at(input).net->driver.cell->type == ctx->id("VCC"))
|
|
return true; // pre-pack high
|
|
return false;
|
|
}
|
|
|
|
// Merge a net into a constant net
|
|
void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constnet, bool constval)
|
|
{
|
|
orig->driver.cell = nullptr;
|
|
for (auto user : orig->users) {
|
|
if (user.cell != nullptr) {
|
|
CellInfo *uc = user.cell;
|
|
if (ctx->verbose)
|
|
log_info("%s user %s\n", orig->name.c_str(ctx), uc->name.c_str(ctx));
|
|
if (is_lut(ctx, uc)) {
|
|
set_lut_input_constant(uc, user.port, constval);
|
|
} else if (is_ff(ctx, uc) && user.port == ctx->id("CE")) {
|
|
uc->params[ctx->id("CEMUX")] = constval ? "1" : "0";
|
|
uc->ports[user.port].net = nullptr;
|
|
} else if (is_carry(ctx, uc)) {
|
|
if (constval &&
|
|
(user.port == id_A0 || user.port == id_A1 || user.port == id_B0 || user.port == id_B1 ||
|
|
user.port == id_C0 || user.port == id_C1 || user.port == id_D0 || user.port == id_D1)) {
|
|
// Input tied high, nothing special to do (bitstream gen will auto-enable tie-high)
|
|
uc->ports[user.port].net = nullptr;
|
|
} else if (!constval) {
|
|
if (user.port == id_A0 || user.port == id_A1 || user.port == id_B0 || user.port == id_B1) {
|
|
// These inputs can be switched to tie-high without consequence
|
|
set_ccu2c_input_constant(uc, user.port, constval);
|
|
} else if (user.port == id_C0 && is_ccu2c_port_high(uc, id_D0)) {
|
|
// Partner must be tied high
|
|
set_ccu2c_input_constant(uc, user.port, constval);
|
|
} else if (user.port == id_D0 && is_ccu2c_port_high(uc, id_C0)) {
|
|
// Partner must be tied high
|
|
set_ccu2c_input_constant(uc, user.port, constval);
|
|
} else if (user.port == id_C1 && is_ccu2c_port_high(uc, id_D1)) {
|
|
// Partner must be tied high
|
|
set_ccu2c_input_constant(uc, user.port, constval);
|
|
} else if (user.port == id_D1 && is_ccu2c_port_high(uc, id_C1)) {
|
|
// Partner must be tied high
|
|
set_ccu2c_input_constant(uc, user.port, constval);
|
|
} else {
|
|
// Not allowed to change to a tie-high
|
|
uc->ports[user.port].net = constnet;
|
|
constnet->users.push_back(user);
|
|
}
|
|
} else {
|
|
uc->ports[user.port].net = constnet;
|
|
constnet->users.push_back(user);
|
|
}
|
|
} else if (is_ff(ctx, uc) && user.port == ctx->id("LSR") &&
|
|
((!constval && str_or_default(uc->params, ctx->id("LSRMUX"), "LSR") == "LSR") ||
|
|
(constval && str_or_default(uc->params, ctx->id("LSRMUX"), "LSR") == "INV"))) {
|
|
uc->ports[user.port].net = nullptr;
|
|
} else if (uc->type == id_DP16KD) {
|
|
if (user.port == id_CLKA || user.port == id_CLKB || user.port == id_RSTA || user.port == id_RSTB ||
|
|
user.port == id_WEA || user.port == id_WEB || user.port == id_CEA || user.port == id_CEB ||
|
|
user.port == id_OCEA || user.port == id_OCEB || user.port == id_CSA0 || user.port == id_CSA1 ||
|
|
user.port == id_CSA2 || user.port == id_CSB0 || user.port == id_CSB1 || user.port == id_CSB2) {
|
|
// Connect to CIB CLK, LSR or CE. Default state is 1
|
|
uc->params[ctx->id(user.port.str(ctx) + "MUX")] = constval ? user.port.str(ctx) : "INV";
|
|
} else {
|
|
// Connected to CIB ABCD. Default state is bitstream configurable
|
|
uc->params[ctx->id(user.port.str(ctx) + "MUX")] = constval ? "1" : "0";
|
|
}
|
|
uc->ports[user.port].net = nullptr;
|
|
} else if (uc->type == id_ALU54B || uc->type == id_MULT18X18D) {
|
|
if (user.port.str(ctx).substr(0, 3) == "CLK" || user.port.str(ctx).substr(0, 2) == "CE" ||
|
|
user.port.str(ctx).substr(0, 3) == "RST" || user.port.str(ctx).substr(0, 3) == "SRO" ||
|
|
user.port.str(ctx).substr(0, 3) == "SRI" || user.port.str(ctx).substr(0, 2) == "RO" ||
|
|
user.port.str(ctx).substr(0, 2) == "MA" || user.port.str(ctx).substr(0, 2) == "MB" ||
|
|
user.port.str(ctx).substr(0, 3) == "CFB" || user.port.str(ctx).substr(0, 3) == "CIN" ||
|
|
user.port.str(ctx).substr(0, 6) == "SOURCE" || user.port.str(ctx).substr(0, 6) == "SIGNED" ||
|
|
user.port.str(ctx).substr(0, 2) == "OP") {
|
|
uc->ports[user.port].net = constnet;
|
|
constnet->users.push_back(user);
|
|
} else {
|
|
// Connected to CIB ABCD. Default state is bitstream configurable
|
|
uc->params[ctx->id(user.port.str(ctx) + "MUX")] = constval ? "1" : "0";
|
|
uc->ports[user.port].net = nullptr;
|
|
}
|
|
} else {
|
|
uc->ports[user.port].net = constnet;
|
|
constnet->users.push_back(user);
|
|
}
|
|
}
|
|
}
|
|
orig->users.clear();
|
|
}
|
|
|
|
// Pack constants (simple implementation)
|
|
void pack_constants()
|
|
{
|
|
log_info("Packing constants..\n");
|
|
|
|
std::unique_ptr<CellInfo> gnd_cell = create_ecp5_cell(ctx, ctx->id("LUT4"), "$PACKER_GND");
|
|
gnd_cell->params[ctx->id("INIT")] = "0";
|
|
std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
|
|
gnd_net->name = ctx->id("$PACKER_GND_NET");
|
|
gnd_net->driver.cell = gnd_cell.get();
|
|
gnd_net->driver.port = ctx->id("Z");
|
|
gnd_cell->ports.at(ctx->id("Z")).net = gnd_net.get();
|
|
|
|
std::unique_ptr<CellInfo> vcc_cell = create_ecp5_cell(ctx, ctx->id("LUT4"), "$PACKER_VCC");
|
|
vcc_cell->params[ctx->id("INIT")] = "65535";
|
|
std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
|
|
vcc_net->name = ctx->id("$PACKER_VCC_NET");
|
|
vcc_net->driver.cell = vcc_cell.get();
|
|
vcc_net->driver.port = ctx->id("Z");
|
|
vcc_cell->ports.at(ctx->id("Z")).net = vcc_net.get();
|
|
|
|
std::vector<IdString> dead_nets;
|
|
|
|
bool gnd_used = false, vcc_used = false;
|
|
|
|
for (auto net : sorted(ctx->nets)) {
|
|
NetInfo *ni = net.second;
|
|
if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) {
|
|
IdString drv_cell = ni->driver.cell->name;
|
|
set_net_constant(ctx, ni, gnd_net.get(), false);
|
|
gnd_used = true;
|
|
dead_nets.push_back(net.first);
|
|
ctx->cells.erase(drv_cell);
|
|
} else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) {
|
|
IdString drv_cell = ni->driver.cell->name;
|
|
set_net_constant(ctx, ni, vcc_net.get(), true);
|
|
vcc_used = true;
|
|
dead_nets.push_back(net.first);
|
|
ctx->cells.erase(drv_cell);
|
|
}
|
|
}
|
|
|
|
if (gnd_used) {
|
|
ctx->cells[gnd_cell->name] = std::move(gnd_cell);
|
|
ctx->nets[gnd_net->name] = std::move(gnd_net);
|
|
}
|
|
if (vcc_used) {
|
|
ctx->cells[vcc_cell->name] = std::move(vcc_cell);
|
|
ctx->nets[vcc_net->name] = std::move(vcc_net);
|
|
}
|
|
|
|
for (auto dn : dead_nets) {
|
|
ctx->nets.erase(dn);
|
|
}
|
|
}
|
|
|
|
void autocreate_empty_port(CellInfo *cell, IdString port)
|
|
{
|
|
if (!cell->ports.count(port)) {
|
|
cell->ports[port].name = port;
|
|
cell->ports[port].net = nullptr;
|
|
cell->ports[port].type = PORT_IN;
|
|
}
|
|
}
|
|
|
|
// Pack EBR
|
|
void pack_ebr()
|
|
{
|
|
// Autoincrement WID (starting from 3 seems to match vendor behaviour?)
|
|
int wid = 3;
|
|
for (auto cell : sorted(ctx->cells)) {
|
|
CellInfo *ci = cell.second;
|
|
if (ci->type == id_DP16KD) {
|
|
// Add ports, even if disconnected, to ensure correct tie-offs
|
|
for (int i = 0; i < 14; i++) {
|
|
autocreate_empty_port(ci, ctx->id("ADA" + std::to_string(i)));
|
|
autocreate_empty_port(ci, ctx->id("ADB" + std::to_string(i)));
|
|
}
|
|
for (int i = 0; i < 18; i++) {
|
|
autocreate_empty_port(ci, ctx->id("DIA" + std::to_string(i)));
|
|
autocreate_empty_port(ci, ctx->id("DIB" + std::to_string(i)));
|
|
}
|
|
for (int i = 0; i < 3; i++) {
|
|
autocreate_empty_port(ci, ctx->id("CSA" + std::to_string(i)));
|
|
autocreate_empty_port(ci, ctx->id("CSB" + std::to_string(i)));
|
|
}
|
|
for (int i = 0; i < 3; i++) {
|
|
autocreate_empty_port(ci, ctx->id("CSA" + std::to_string(i)));
|
|
autocreate_empty_port(ci, ctx->id("CSB" + std::to_string(i)));
|
|
}
|
|
|
|
autocreate_empty_port(ci, id_CLKA);
|
|
autocreate_empty_port(ci, id_CEA);
|
|
autocreate_empty_port(ci, id_OCEA);
|
|
autocreate_empty_port(ci, id_WEA);
|
|
autocreate_empty_port(ci, id_RSTA);
|
|
|
|
autocreate_empty_port(ci, id_CLKB);
|
|
autocreate_empty_port(ci, id_CEB);
|
|
autocreate_empty_port(ci, id_OCEB);
|
|
autocreate_empty_port(ci, id_WEB);
|
|
autocreate_empty_port(ci, id_RSTB);
|
|
|
|
ci->attrs[ctx->id("WID")] = std::to_string(wid++);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Pack DSPs
|
|
void pack_dsps()
|
|
{
|
|
for (auto cell : sorted(ctx->cells)) {
|
|
CellInfo *ci = cell.second;
|
|
if (ci->type == id_MULT18X18D) {
|
|
// Add ports, even if disconnected, to ensure correct tie-offs
|
|
for (auto sig : {"CLK", "CE", "RST"})
|
|
for (int i = 0; i < 4; i++)
|
|
autocreate_empty_port(ci, ctx->id(sig + std::to_string(i)));
|
|
for (auto sig : {"SIGNED", "SOURCE"})
|
|
for (auto c : {"A", "B"})
|
|
autocreate_empty_port(ci, ctx->id(sig + std::string(c)));
|
|
for (auto port : {"A", "B", "C"})
|
|
for (int i = 0; i < 18; i++)
|
|
autocreate_empty_port(ci, ctx->id(port + std::to_string(i)));
|
|
for (auto port : {"SRIA", "SRIB"})
|
|
for (int i = 0; i < 18; i++)
|
|
autocreate_empty_port(ci, ctx->id(port + std::to_string(i)));
|
|
} else if (ci->type == id_ALU54B) {
|
|
for (auto sig : {"CLK", "CE", "RST"})
|
|
for (int i = 0; i < 4; i++)
|
|
autocreate_empty_port(ci, ctx->id(sig + std::to_string(i)));
|
|
autocreate_empty_port(ci, id_SIGNEDIA);
|
|
autocreate_empty_port(ci, id_SIGNEDIB);
|
|
autocreate_empty_port(ci, id_SIGNEDCIN);
|
|
for (auto port : {"A", "B", "MA", "MB"})
|
|
for (int i = 0; i < 36; i++)
|
|
autocreate_empty_port(ci, ctx->id(port + std::to_string(i)));
|
|
for (auto port : {"C", "CFB", "CIN"})
|
|
for (int i = 0; i < 54; i++)
|
|
autocreate_empty_port(ci, ctx->id(port + std::to_string(i)));
|
|
for (int i = 0; i < 11; i++)
|
|
autocreate_empty_port(ci, ctx->id("OP" + std::to_string(i)));
|
|
}
|
|
}
|
|
}
|
|
|
|
public:
|
|
void pack()
|
|
{
|
|
pack_io();
|
|
pack_ebr();
|
|
pack_dsps();
|
|
pack_constants();
|
|
pack_dram();
|
|
pack_carries();
|
|
find_lutff_pairs();
|
|
pack_lut5s();
|
|
pair_luts();
|
|
pack_lut_pairs();
|
|
pack_remaining_luts();
|
|
pack_remaining_ffs();
|
|
ctx->check();
|
|
}
|
|
|
|
private:
|
|
Context *ctx;
|
|
|
|
std::unordered_set<IdString> packed_cells;
|
|
std::vector<std::unique_ptr<CellInfo>> new_cells;
|
|
|
|
struct SliceUsage
|
|
{
|
|
bool lut0_used = false, lut1_used = false;
|
|
bool ccu2_used = false, dpram_used = false, ramw_used = false;
|
|
bool ff0_used = false, ff1_used = false;
|
|
bool mux5_used = false, muxx_used = false;
|
|
};
|
|
|
|
std::unordered_map<IdString, SliceUsage> sliceUsage;
|
|
std::unordered_map<IdString, IdString> lutffPairs;
|
|
std::unordered_map<IdString, IdString> fflutPairs;
|
|
std::unordered_map<IdString, IdString> lutPairs;
|
|
};
|
|
// Main pack function
|
|
bool Arch::pack()
|
|
{
|
|
Context *ctx = getCtx();
|
|
try {
|
|
log_break();
|
|
Ecp5Packer(ctx).pack();
|
|
log_info("Checksum: 0x%08x\n", ctx->checksum());
|
|
assignArchInfo();
|
|
return true;
|
|
} catch (log_execution_error_exception) {
|
|
assignArchInfo();
|
|
return false;
|
|
}
|
|
}
|
|
|
|
void Arch::assignArchInfo()
|
|
{
|
|
for (auto cell : sorted(cells)) {
|
|
CellInfo *ci = cell.second;
|
|
if (ci->type == id_TRELLIS_SLICE) {
|
|
|
|
ci->sliceInfo.using_dff = false;
|
|
if (ci->ports.count(id_Q0) && ci->ports[id_Q0].net != nullptr)
|
|
ci->sliceInfo.using_dff = true;
|
|
if (ci->ports.count(id_Q1) && ci->ports[id_Q1].net != nullptr)
|
|
ci->sliceInfo.using_dff = true;
|
|
|
|
if (ci->ports.count(id_CLK) && ci->ports[id_CLK].net != nullptr)
|
|
ci->sliceInfo.clk_sig = ci->ports[id_CLK].net->name;
|
|
else
|
|
ci->sliceInfo.clk_sig = IdString();
|
|
|
|
if (ci->ports.count(id_LSR) && ci->ports[id_LSR].net != nullptr)
|
|
ci->sliceInfo.lsr_sig = ci->ports[id_LSR].net->name;
|
|
else
|
|
ci->sliceInfo.lsr_sig = IdString();
|
|
|
|
ci->sliceInfo.clkmux = id(str_or_default(ci->params, id_CLKMUX, "CLK"));
|
|
ci->sliceInfo.lsrmux = id(str_or_default(ci->params, id_LSRMUX, "LSR"));
|
|
ci->sliceInfo.srmode = id(str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
|
|
}
|
|
}
|
|
}
|
|
|
|
NEXTPNR_NAMESPACE_END
|