nextpnr/himbaechel/uarch/gowin
YRabbit 4d5c48ad83 Gowin. Fix DSP MULT36X36
When multiplying 36 bits by 36 bits using four 18x18 multipliers, the
sign bits of the higher 18-bit parts of the multipliers were correctly
switched, but what was incorrect was leaving the sign bits of the lower
parts of the multipliers uninitialized. They now connect to VSS.

Addresses https://github.com/YosysHQ/apicula/issues/242

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-04-19 11:55:39 +02:00
..
CMakeLists.txt gowin: Himbaechel. Add GW1NZ-1 BSRAM. 2023-11-26 13:08:09 +01:00
constids.inc Gowin. Fix DSP MULT36X36 2024-04-19 11:55:39 +02:00
cst.cc gowin: Himbaechel. Extend clock router 2023-09-08 09:15:35 +02:00
cst.h gowin: Himbaechel. Add constraint file processing. 2023-08-31 08:28:09 +02:00
globals.cc gowin: Add support for DSP primitives. 2024-03-22 09:47:10 +00:00
globals.h gowin: Himbaechel. Add a clock router. 2023-08-31 08:28:09 +02:00
gowin_arch_gen.py Gowin. Fix DSP MULT36X36 2024-04-19 11:55:39 +02:00
gowin_utils.cc Gowin. Add PLL pads. 2024-04-09 10:15:42 +02:00
gowin_utils.h Gowin. Add PLL pads. 2024-04-09 10:15:42 +02:00
gowin.cc gowin: BUGFIX fix typo 2024-03-22 09:49:01 +00:00
gowin.h Gowin. Add PLL pads. 2024-04-09 10:15:42 +02:00
pack.cc Gowin. Fix DSP MULT36X36 2024-04-19 11:55:39 +02:00
pack.h gowin: Himbaechel. Add ALU. 2023-08-31 08:28:09 +02:00