4d5c48ad83
When multiplying 36 bits by 36 bits using four 18x18 multipliers, the sign bits of the higher 18-bit parts of the multipliers were correctly switched, but what was incorrect was leaving the sign bits of the lower parts of the multipliers uninitialized. They now connect to VSS. Addresses https://github.com/YosysHQ/apicula/issues/242 Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
1064 lines
42 KiB
Python
1064 lines
42 KiB
Python
from os import path
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import sys
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import importlib.resources
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import pickle
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import gzip
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import re
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import argparse
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sys.path.append(path.join(path.dirname(__file__), "../.."))
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from himbaechel_dbgen.chip import *
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from apycula import chipdb
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# Bel flags
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BEL_FLAG_SIMPLE_IO = 0x100
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# Chip flags
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CHIP_HAS_SP32 = 0x1
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# Z of the bels
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# sync with C++ part!
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LUT0_Z = 0 # z(DFFx) = z(LUTx) + 1
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LUT7_Z = 14
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MUX20_Z = 16
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MUX21_Z = 18
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MUX23_Z = 22
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MUX27_Z = 29
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ALU0_Z = 30 # : 35, 6 ALUs
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RAMW_Z = 36 # RAM16SDP4
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IOBA_Z = 50
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IOBB_Z = 51
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IOLOGICA_Z = 70
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IDES16_Z = 74
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OSER16_Z = 75
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BUFG_Z = 76 # : 81 reserve just in case
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BSRAM_Z = 100
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OSC_Z = 274
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PLL_Z = 275
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GSR_Z = 276
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VCC_Z = 277
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GND_Z = 278
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DSP_Z = 509
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DSP_0_Z = 511 # DSP macro 0
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PADD18_0_0_Z = 512
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PADD9_0_0_Z = 512 + 1
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PADD9_0_1_Z = 512 + 2
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PADD18_0_1_Z = 516
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PADD9_0_2_Z = 516 + 1
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PADD9_0_3_Z = 516 + 2
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MULT18X18_0_0_Z = 520
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MULT9X9_0_0_Z = 520 + 1
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MULT9X9_0_1_Z = 520 + 2
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MULT18X18_0_1_Z = 524
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MULT9X9_0_2_Z = 524 + 1
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MULT9X9_0_3_Z = 524 + 2
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ALU54D_0_Z = 524 + 3
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MULTALU18X18_0_Z = 528
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MULTALU36X18_0_Z = 528 + 1
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MULTADDALU18X18_0_Z = 528 + 2
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MULT36X36_Z = 528 + 3
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DSP_1_Z = 543 # DSP macro 1
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PADD18_1_0_Z = 544
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PADD9_1_0_Z = 544 + 1
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PADD9_1_1_Z = 544 + 2
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PADD18_1_1_Z = 548
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PADD9_1_2_Z = 548 + 1
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PADD9_1_3_Z = 548 + 2
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MULT18X18_1_0_Z = 552
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MULT9X9_1_0_Z = 552 + 1
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MULT9X9_1_1_Z = 552 + 2
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MULT18X18_1_1_Z = 556
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MULT9X9_1_2_Z = 556 + 1
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MULT9X9_1_3_Z = 556 + 2
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ALU54D_1_Z = 556 + 3
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MULTALU18X18_1_Z = 560
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MULTALU36X18_1_Z = 560 + 1
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MULTADDALU18X18_1_Z = 560 + 2
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# =======================================
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# Chipdb additional info
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# =======================================
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@dataclass
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class TileExtraData(BBAStruct):
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tile_class: IdString # The general functionality of the slightly different tiles,
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# let's say the behavior of LUT+DFF in the tiles are completely identical,
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# but one of them also contains clock-wire switches,
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# then we assign them to the same LOGIC class.
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io16_x_off: int = 0 # OSER16/IDES16 offsets to the aux cell
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io16_y_off: int = 0
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def serialise_lists(self, context: str, bba: BBAWriter):
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pass
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def serialise(self, context: str, bba: BBAWriter):
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bba.u32(self.tile_class.index)
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bba.u16(self.io16_x_off)
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bba.u16(self.io16_y_off)
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@dataclass
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class BottomIOCnd(BBAStruct):
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wire_a_net: IdString
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wire_b_net: IdString
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def serialise_lists(self, context: str, bba: BBAWriter):
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pass
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def serialise(self, context: str, bba: BBAWriter):
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bba.u32(self.wire_a_net.index)
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bba.u32(self.wire_b_net.index)
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@dataclass
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class BottomIO(BBAStruct):
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conditions: list[BottomIOCnd] = field(default_factory = list)
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def serialise_lists(self, context: str, bba: BBAWriter):
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bba.label(f"{context}_conditions")
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for i, cnd in enumerate(self.conditions):
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cnd.serialise(f"{context}_cnd{i}", bba)
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def serialise(self, context: str, bba: BBAWriter):
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bba.slice(f"{context}_conditions", len(self.conditions))
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@dataclass
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class ChipExtraData(BBAStruct):
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strs: StringPool
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flags: int
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bottom_io: BottomIO
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diff_io_types: list[IdString] = field(default_factory = list)
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def create_bottom_io(self):
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self.bottom_io = BottomIO()
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def add_bottom_io_cnd(self, net_a: str, net_b: str):
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self.bottom_io.conditions.append(BottomIOCnd(self.strs.id(net_a), self.strs.id(net_b)))
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def add_diff_io_type(self, diff_type: str):
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self.diff_io_types.append(self.strs.id(diff_type))
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def serialise_lists(self, context: str, bba: BBAWriter):
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self.bottom_io.serialise_lists(f"{context}_bottom_io", bba)
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bba.label(f"{context}_diff_io_types")
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for i, diff_io_type in enumerate(self.diff_io_types):
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bba.u32(diff_io_type.index)
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def serialise(self, context: str, bba: BBAWriter):
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bba.u32(self.flags)
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self.bottom_io.serialise(f"{context}_bottom_io", bba)
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bba.slice(f"{context}_diff_io_types", len(self.diff_io_types))
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@dataclass
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class PadExtraData(BBAStruct):
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# Which PLL does this pad belong to.
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pll_tile: IdString
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pll_bel: IdString
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pll_type: IdString
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def serialise_lists(self, context: str, bba: BBAWriter):
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pass
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def serialise(self, context: str, bba: BBAWriter):
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bba.u32(self.pll_tile.index)
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bba.u32(self.pll_bel.index)
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bba.u32(self.pll_type.index)
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# Unique features of the tiletype
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class TypeDesc:
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def __init__(self, dups, tiletype = '', extra_func = None, sfx = 0):
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self.tiletype = tiletype
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self.extra_func = extra_func
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self.dups = dups
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self.sfx = sfx
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created_tiletypes = {}
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# u-turn at the rim
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uturnlut = {'N': 'S', 'S': 'N', 'E': 'W', 'W': 'E'}
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def uturn(db: chipdb, x: int, y: int, wire: str):
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m = re.match(r"([NESW])([128]\d)(\d)", wire)
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if m:
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direction, num, segment = m.groups()
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# wires wrap around the edges
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# assumes 0-based indexes
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if y < 0:
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y = -1 - y
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direction = uturnlut[direction]
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if x < 0:
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x = -1 - x
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direction = uturnlut[direction]
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if y > db.rows - 1:
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y = 2 * db.rows - 1 - y
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direction = uturnlut[direction]
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if x > db.cols - 1:
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x = 2 * db.cols - 1 - x
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direction = uturnlut[direction]
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wire = f'{direction}{num}{segment}'
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return (x, y, wire)
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def create_nodes(chip: Chip, db: chipdb):
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# : (x, y)
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dirs = { 'N': (0, -1), 'S': (0, 1), 'W': (-1, 0), 'E': (1, 0) }
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X = db.cols
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Y = db.rows
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global_nodes = {}
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for y in range(Y):
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for x in range(X):
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nodes = []
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tt = chip.tile_type_at(x, y)
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extra_tile_data = tt.extra_data
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# SN and EW
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for i in [1, 2]:
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nodes.append([NodeWire(x, y, f'SN{i}0'),
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NodeWire(*uturn(db, x, y - 1, f'N1{i}1')),
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NodeWire(*uturn(db, x, y + 1, f'S1{i}1'))])
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nodes.append([NodeWire(x, y, f'EW{i}0'),
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NodeWire(*uturn(db, x - 1, y, f'W1{i}1')),
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NodeWire(*uturn(db, x + 1, y, f'E1{i}1'))])
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for d, offs in dirs.items():
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# 1-hop
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for i in [0, 3]:
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nodes.append([NodeWire(x, y, f'{d}1{i}0'),
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NodeWire(*uturn(db, x + offs[0], y + offs[1], f'{d}1{i}1'))])
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# 2-hop
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for i in range(8):
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nodes.append([NodeWire(x, y, f'{d}2{i}0'),
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NodeWire(*uturn(db, x + offs[0], y + offs[1], f'{d}2{i}1')),
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NodeWire(*uturn(db, x + offs[0] * 2, y + offs[1] * 2, f'{d}2{i}2'))])
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# 4-hop
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for i in range(4):
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nodes.append([NodeWire(x, y, f'{d}8{i}0'),
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NodeWire(*uturn(db, x + offs[0] * 4, y + offs[1] * 4, f'{d}8{i}4')),
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NodeWire(*uturn(db, x + offs[0] * 8, y + offs[1] * 8, f'{d}8{i}8'))])
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# I0 for MUX2_LUT8
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if (x < X - 1 and extra_tile_data.tile_class == chip.strs.id('LOGIC')
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and chip.tile_type_at(x + 1, y).extra_data.tile_class == chip.strs.id('LOGIC')):
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nodes.append([NodeWire(x, y, 'OF30'),
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NodeWire(x + 1, y, 'OF3')])
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# ALU
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if extra_tile_data.tile_class == chip.strs.id('LOGIC'):
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# local carry chain
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for i in range(5):
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nodes.append([NodeWire(x, y, f'COUT{i}'),
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NodeWire(x, y, f'CIN{i + 1}')]);
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# gobal carry chain
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if x > 1 and chip.tile_type_at(x - 1, y).extra_data.tile_class == chip.strs.id('LOGIC'):
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nodes.append([NodeWire(x, y, f'CIN0'),
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NodeWire(x - 1, y, f'COUT5')])
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for node in nodes:
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chip.add_node(node)
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# VCC and VSS sources in the all tiles
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global_nodes.setdefault('GND', []).append(NodeWire(x, y, 'VSS'))
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global_nodes.setdefault('VCC', []).append(NodeWire(x, y, 'VCC'))
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# add nodes from the apicula db
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for node_name, node_hdr in db.nodes.items():
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wire_type, node = node_hdr
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if len(node) < 2:
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continue
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for y, x, wire in node:
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if wire_type:
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if not chip.tile_type_at(x, y).has_wire(wire):
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chip.tile_type_at(x, y).create_wire(wire, wire_type)
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else:
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chip.tile_type_at(x, y).set_wire_type(wire, wire_type)
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new_node = NodeWire(x, y, wire)
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gl_nodes = global_nodes.setdefault(node_name, [])
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if new_node not in gl_nodes:
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gl_nodes.append(NodeWire(x, y, wire))
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for name, node in global_nodes.items():
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chip.add_node(node)
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def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
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def get_wire_type(name):
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if name in {'XD0', 'XD1', 'XD2', 'XD3', 'XD4', 'XD5',}:
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return "X0"
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return ""
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for dst, srcs in db.grid[y][x].pips.items():
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if not tt.has_wire(dst):
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tt.create_wire(dst, get_wire_type(dst))
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for src in srcs.keys():
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if not tt.has_wire(src):
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tt.create_wire(src, get_wire_type(src))
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tt.create_pip(src, dst)
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# clock wires
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for dst, srcs in db.grid[y][x].pure_clock_pips.items():
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if not tt.has_wire(dst):
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tt.create_wire(dst, "GLOBAL_CLK")
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for src in srcs.keys():
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if not tt.has_wire(src):
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tt.create_wire(src, "GLOBAL_CLK")
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tt.create_pip(src, dst)
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def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
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if (y, x) not in db.hclk_pips:
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return
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# hclk wires
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for dst, srcs in db.hclk_pips[y, x].items():
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if not tt.has_wire(dst):
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tt.create_wire(dst, "HCLK")
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for src in srcs.keys():
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if not tt.has_wire(src):
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tt.create_wire(src, "HCLK")
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tt.create_pip(src, dst)
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def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
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if (y, x) not in db.extra_func:
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return
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for func, desc in db.extra_func[(y, x)].items():
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if func == 'osc':
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osc_type = desc['type']
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portmap = db.grid[y][x].bels[osc_type].portmap
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for port, wire in portmap.items():
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tt.create_wire(wire, port)
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bel = tt.create_bel(osc_type, osc_type, z = OSC_Z)
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for port, wire in portmap.items():
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if 'OUT' in port:
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tt.add_bel_pin(bel, port, wire, PinType.OUTPUT)
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else:
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tt.add_bel_pin(bel, port, wire, PinType.INPUT)
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elif func == 'gsr':
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wire = desc['wire']
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tt.create_wire(wire, "GSRI")
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bel = tt.create_bel("GSR", "GSR", z = GSR_Z)
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tt.add_bel_pin(bel, "GSRI", wire, PinType.INPUT)
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if func == 'io16':
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role = desc['role']
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if role == 'MAIN':
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y_off, x_off = desc['pair']
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tt.extra_data.io16_x_off = x_off
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tt.extra_data.io16_y_off = y_off
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for io_type, z in {('IDES16', IDES16_Z), ('OSER16', OSER16_Z)}:
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bel = tt.create_bel(io_type, io_type, z = z)
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portmap = db.grid[y][x].bels[io_type].portmap
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for port, wire in portmap.items():
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if port == 'FCLK': # XXX compatibility
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wire = 'FCLKA'
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if not tt.has_wire(wire):
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if port in {'CLK', 'PCLK'}:
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tt.create_wire(wire, "TILE_CLK")
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else:
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tt.create_wire(wire, "IOL_PORT")
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if 'OUT' in port:
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tt.add_bel_pin(bel, port, wire, PinType.OUTPUT)
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else:
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tt.add_bel_pin(bel, port, wire, PinType.INPUT)
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if func == 'buf':
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for buf_type, wires in desc.items():
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for i, wire in enumerate(wires):
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if not tt.has_wire(wire):
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tt.create_wire(wire, "TILE_CLK")
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wire_out = f'{buf_type}{i}_O'
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tt.create_wire(wire_out, "TILE_CLK")
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# XXX make Z from buf_type
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bel = tt.create_bel(f'{buf_type}{i}', buf_type, z = BUFG_Z + i)
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bel.flags = BEL_FLAG_GLOBAL
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tt.add_bel_pin(bel, "I", wire, PinType.INPUT)
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tt.add_bel_pin(bel, "O", wire_out, PinType.OUTPUT)
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def create_tiletype(create_func, chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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has_extra_func = (y, x) in db.extra_func
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# (found, TypeDesc)
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def find_or_make_dup():
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for d in created_tiletypes[ttyp].dups:
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if has_extra_func and d.extra_func == db.extra_func[(y, x)]:
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return (True, d)
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elif not has_extra_func and not d.extra_func:
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return (True, d)
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sfx = len(created_tiletypes[ttyp].dups) + 1
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if has_extra_func:
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tdesc = TypeDesc(extra_func = db.extra_func[(y, x)], sfx = sfx, dups = [])
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else:
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tdesc = TypeDesc(sfx = sfx, dups = [])
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created_tiletypes[ttyp].dups.append(tdesc)
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return (False, tdesc)
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old_type = False
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if ttyp not in created_tiletypes:
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# new type
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if has_extra_func:
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tdesc = TypeDesc(extra_func = db.extra_func[(y, x)], dups = [])
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else:
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tdesc = TypeDesc(dups = [])
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created_tiletypes.update({ttyp: tdesc})
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else:
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# find similar
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if has_extra_func:
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if created_tiletypes[ttyp].extra_func == db.extra_func[(y, x)]:
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tdesc = created_tiletypes[ttyp]
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old_type = True
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else:
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old_type, tdesc = find_or_make_dup()
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elif not created_tiletypes[ttyp].extra_func:
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tdesc = created_tiletypes[ttyp]
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old_type = True
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else:
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old_type, tdesc = find_or_make_dup()
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if old_type:
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chip.set_tile_type(x, y, tdesc.tiletype)
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return
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tt = create_func(chip, db, x, y, ttyp, tdesc)
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create_extra_funcs(tt, db, x, y)
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create_hclk_switch_matrix(tt, db, x, y)
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create_switch_matrix(tt, db, x, y)
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chip.set_tile_type(x, y, tdesc.tiletype)
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def add_port_wire(tt, bel, portmap, name, wire_type, port_type, pin_name = None):
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wire = portmap[name]
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if not tt.has_wire(wire):
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if name.startswith('CLK'):
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tt.create_wire(wire, "TILE_CLK")
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else:
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tt.create_wire(wire, wire_type)
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if pin_name:
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tt.add_bel_pin(bel, pin_name, wire, port_type)
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else:
|
|
tt.add_bel_pin(bel, name, wire, port_type)
|
|
|
|
def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
|
|
typename = "NULL"
|
|
tiletype = f"{typename}_{ttyp}"
|
|
if tdesc.sfx != 0:
|
|
tiletype += f"_{tdesc.sfx}"
|
|
tt = chip.create_tile_type(tiletype)
|
|
tt.extra_data = TileExtraData(chip.strs.id(typename))
|
|
tdesc.tiletype = tiletype
|
|
return tt
|
|
|
|
# responsible nodes, there will be IO banks, configuration, etc.
|
|
def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
|
|
typename = "CORNER"
|
|
tiletype = f"{typename}_{ttyp}"
|
|
if tdesc.sfx != 0:
|
|
tiletype += f"_{tdesc.sfx}"
|
|
tt = chip.create_tile_type(tiletype)
|
|
tt.extra_data = TileExtraData(chip.strs.id(typename))
|
|
|
|
if x == 0 and y == 0:
|
|
# GND is the logic low level generator
|
|
tt.create_wire('VSS', 'GND')
|
|
gnd = tt.create_bel('GND', 'GND', z = GND_Z)
|
|
tt.add_bel_pin(gnd, "G", "VSS", PinType.OUTPUT)
|
|
# VCC is the logic high level generator
|
|
tt.create_wire('VCC', 'VCC')
|
|
gnd = tt.create_bel('VCC', 'VCC', z = VCC_Z)
|
|
tt.add_bel_pin(gnd, "V", "VCC", PinType.OUTPUT)
|
|
|
|
tdesc.tiletype = tiletype
|
|
return tt
|
|
|
|
|
|
# IO
|
|
def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
|
|
typename = "IO"
|
|
tiletype = f"{typename}_{ttyp}"
|
|
if tdesc.sfx != 0:
|
|
tiletype += f"_{tdesc.sfx}"
|
|
tt = chip.create_tile_type(tiletype)
|
|
tt.extra_data = TileExtraData(chip.strs.id(typename))
|
|
|
|
simple_io = y in db.simplio_rows and chip.name in {'GW1N-1', 'GW1NZ-1', 'GW1N-4'}
|
|
if simple_io:
|
|
rng = 10
|
|
else:
|
|
rng = 2
|
|
for i in range(rng):
|
|
name = 'IOB' + 'ABCDEFGHIJ'[i]
|
|
# XXX some IOBs excluded from generic chipdb for some reason
|
|
if name not in db.grid[y][x].bels:
|
|
continue
|
|
# wires
|
|
portmap = db.grid[y][x].bels[name].portmap
|
|
tt.create_wire(portmap['I'], "IO_I")
|
|
tt.create_wire(portmap['O'], "IO_O")
|
|
tt.create_wire(portmap['OE'], "IO_OE")
|
|
# bels
|
|
io = tt.create_bel(name, "IOB", z = IOBA_Z + i)
|
|
if simple_io and chip.name in {'GW1N-1'}:
|
|
io.flags |= BEL_FLAG_SIMPLE_IO
|
|
tt.add_bel_pin(io, "I", portmap['I'], PinType.INPUT)
|
|
tt.add_bel_pin(io, "OEN", portmap['OE'], PinType.INPUT)
|
|
tt.add_bel_pin(io, "O", portmap['O'], PinType.OUTPUT)
|
|
# bottom io
|
|
if 'BOTTOM_IO_PORT_A' in portmap:
|
|
if not tt.has_wire(portmap['BOTTOM_IO_PORT_A']):
|
|
tt.create_wire(portmap['BOTTOM_IO_PORT_A'], "IO_I")
|
|
tt.create_wire(portmap['BOTTOM_IO_PORT_B'], "IO_I")
|
|
tt.add_bel_pin(io, "BOTTOM_IO_PORT_A", portmap['BOTTOM_IO_PORT_A'], PinType.INPUT)
|
|
tt.add_bel_pin(io, "BOTTOM_IO_PORT_B", portmap['BOTTOM_IO_PORT_B'], PinType.INPUT)
|
|
# create IOLOGIC bels if any
|
|
for idx, name in {(IOLOGICA_Z, 'IOLOGICA'), (IOLOGICA_Z + 1, 'IOLOGICB')}:
|
|
if name not in db.grid[y][x].bels:
|
|
continue
|
|
for off, io_type in {(0, 'O'), (2, 'I')}:
|
|
iol = tt.create_bel(f"{name}{io_type}", f"IOLOGIC{io_type}", z = idx + off)
|
|
for port, wire in db.grid[y][x].bels[name].portmap.items():
|
|
if port == 'FCLK': # XXX compatibility
|
|
wire = f'FCLK{name[-1]}'
|
|
if not tt.has_wire(wire):
|
|
if port in {'CLK', 'PCLK'}:
|
|
tt.create_wire(wire, "TILE_CLK")
|
|
else:
|
|
tt.create_wire(wire, "IOL_PORT")
|
|
if port in {'Q', 'Q0', 'Q1', 'Q2', 'Q3', 'Q4', 'Q5', 'Q6', 'Q7', 'Q8', 'Q9', 'DF', 'LAG', 'LEAD'}:
|
|
tt.add_bel_pin(iol, port, wire, PinType.OUTPUT)
|
|
else:
|
|
tt.add_bel_pin(iol, port, wire, PinType.INPUT)
|
|
tdesc.tiletype = tiletype
|
|
return tt
|
|
|
|
# logic: luts, dffs, alu etc
|
|
def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
|
|
typename = "LOGIC"
|
|
tiletype = f"{typename}_{ttyp}"
|
|
if tdesc.sfx != 0:
|
|
tiletype += f"_{tdesc.sfx}"
|
|
tt = chip.create_tile_type(tiletype)
|
|
tt.extra_data = TileExtraData(chip.strs.id(typename))
|
|
|
|
lut_inputs = ['A', 'B', 'C', 'D']
|
|
# setup LUT wires
|
|
for i in range(8):
|
|
for inp_name in lut_inputs:
|
|
tt.create_wire(f"{inp_name}{i}", "LUT_INPUT")
|
|
tt.create_wire(f"F{i}", "LUT_OUT")
|
|
# experimental. the wire is false - it is assumed that DFF is always
|
|
# connected to the LUT's output F{i}, but we can place primitives
|
|
# arbitrarily and create a pass-through LUT afterwards.
|
|
# just out of curiosity
|
|
tt.create_wire(f"XD{i}", "FF_INPUT")
|
|
tt.create_wire(f"Q{i}", "FF_OUT")
|
|
# setup DFF wires
|
|
for j in range(3):
|
|
tt.create_wire(f"CLK{j}", "TILE_CLK")
|
|
tt.create_wire(f"LSR{j}", "TILE_LSR")
|
|
tt.create_wire(f"CE{j}", "TILE_CE")
|
|
# setup MUX2 wires
|
|
for j in range(8):
|
|
tt.create_wire(f"OF{j}", "MUX_OUT")
|
|
tt.create_wire(f"SEL{j}", "MUX_SEL")
|
|
tt.create_wire("OF30", "MUX_OUT")
|
|
# setup ALU wires
|
|
for j in range(6):
|
|
tt.create_wire(f"CIN{j}", "ALU_CIN")
|
|
tt.create_wire(f"COUT{j}", "ALU_COUT")
|
|
|
|
# create logic cells
|
|
for i in range(8):
|
|
# LUT
|
|
lut = tt.create_bel(f"LUT{i}", "LUT4", z = (i * 2 + 0))
|
|
for j, inp_name in enumerate(lut_inputs):
|
|
tt.add_bel_pin(lut, f"I{j}", f"{inp_name}{i}", PinType.INPUT)
|
|
tt.add_bel_pin(lut, "F", f"F{i}", PinType.OUTPUT)
|
|
if i < 6:
|
|
# FF data can come from LUT output, but we pretend that we can use
|
|
# any LUT input
|
|
tt.create_pip(f"F{i}", f"XD{i}")
|
|
for inp_name in lut_inputs:
|
|
tt.create_pip(f"{inp_name}{i}", f"XD{i}")
|
|
# FF
|
|
ff = tt.create_bel(f"DFF{i}", "DFF", z =(i * 2 + 1))
|
|
tt.add_bel_pin(ff, "D", f"XD{i}", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "CLK", f"CLK{i // 2}", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "Q", f"Q{i}", PinType.OUTPUT)
|
|
tt.add_bel_pin(ff, "SET", f"LSR{i // 2}", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "RESET", f"LSR{i // 2}", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "PRESET", f"LSR{i // 2}", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "CLEAR", f"LSR{i // 2}", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "CE", f"CE{i // 2}", PinType.INPUT)
|
|
|
|
# ALU
|
|
ff = tt.create_bel(f"ALU{i}", "ALU", z = i + ALU0_Z)
|
|
tt.add_bel_pin(ff, "SUM", f"F{i}", PinType.OUTPUT)
|
|
tt.add_bel_pin(ff, "COUT", f"COUT{i}", PinType.OUTPUT)
|
|
tt.add_bel_pin(ff, "CIN", f"CIN{i}", PinType.INPUT)
|
|
# pinout for the ADDSUB ALU mode
|
|
tt.add_bel_pin(ff, "I0", f"A{i}", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "I1", f"B{i}", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "I2", f"C{i}", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "I3", f"D{i}", PinType.INPUT)
|
|
|
|
# wide luts
|
|
for i in range(4):
|
|
ff = tt.create_bel(f"MUX{i * 2}", "MUX2_LUT5", z = MUX20_Z + i * 4)
|
|
tt.add_bel_pin(ff, "I0", f"F{i * 2}", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "I1", f"F{i * 2 + 1}", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "O", f"OF{i * 2}", PinType.OUTPUT)
|
|
tt.add_bel_pin(ff, "S0", f"SEL{i * 2}", PinType.INPUT)
|
|
for i in range(2):
|
|
ff = tt.create_bel(f"MUX{i * 4 + 1}", "MUX2_LUT6", z = MUX21_Z + i * 8)
|
|
tt.add_bel_pin(ff, "I0", f"OF{i * 4 + 2}", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "I1", f"OF{i * 4}", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "O", f"OF{i * 4 + 1}", PinType.OUTPUT)
|
|
tt.add_bel_pin(ff, "S0", f"SEL{i * 4 + 1}", PinType.INPUT)
|
|
ff = tt.create_bel(f"MUX3", "MUX2_LUT7", z = MUX23_Z)
|
|
tt.add_bel_pin(ff, "I0", f"OF5", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "I1", f"OF1", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "O", f"OF3", PinType.OUTPUT)
|
|
tt.add_bel_pin(ff, "S0", f"SEL3", PinType.INPUT)
|
|
ff = tt.create_bel(f"MUX7", "MUX2_LUT8", z = MUX27_Z)
|
|
tt.add_bel_pin(ff, "I0", f"OF30", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "I1", f"OF3", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "O", f"OF7", PinType.OUTPUT)
|
|
tt.add_bel_pin(ff, "S0", f"SEL7", PinType.INPUT)
|
|
|
|
tdesc.tiletype = tiletype
|
|
return tt
|
|
|
|
def create_ssram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
|
|
# SSRAM is LUT based, so it's logic-like
|
|
tt = create_logic_tiletype(chip, db, x, y, ttyp, tdesc)
|
|
|
|
lut_inputs = ['A', 'B', 'C', 'D']
|
|
ff = tt.create_bel(f"RAM16SDP4", "RAM16SDP4", z = RAMW_Z)
|
|
for i in range(4):
|
|
tt.add_bel_pin(ff, f"DI[{i}]", f"{lut_inputs[i]}5", PinType.INPUT)
|
|
tt.add_bel_pin(ff, f"WAD[{i}]", f"{lut_inputs[i]}4", PinType.INPUT)
|
|
# RAD[0] is assumed to be connected to A3, A2, A1 and A0. But
|
|
# for now we connect it only to A0, the others will be connected
|
|
# directly during packing. RAD[1...3] - similarly.
|
|
tt.add_bel_pin(ff, f"RAD[{i}]", f"{lut_inputs[i]}0", PinType.INPUT)
|
|
tt.add_bel_pin(ff, f"DO[{i}]", f"F{i}", PinType.OUTPUT)
|
|
|
|
tt.add_bel_pin(ff, "CLK", "CLK2", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "CE", "CE2", PinType.INPUT)
|
|
tt.add_bel_pin(ff, "WRE", "LSR2", PinType.INPUT)
|
|
return tt
|
|
|
|
# BSRAM
|
|
_bsram_inputs = {'CLK', 'OCE', 'CE', 'RESET', 'WRE'}
|
|
def create_bsram_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
|
|
typename = "BSRAM"
|
|
tiletype = f"{typename}_{ttyp}"
|
|
if tdesc.sfx != 0:
|
|
tiletype += f"_{tdesc.sfx}"
|
|
tt = chip.create_tile_type(tiletype)
|
|
tt.extra_data = TileExtraData(chip.strs.id(typename))
|
|
|
|
portmap = db.grid[y][x].bels['BSRAM'].portmap
|
|
bsram = tt.create_bel("BSRAM", "BSRAM", z = BSRAM_Z)
|
|
|
|
|
|
for sfx in {'', 'A', 'B'}:
|
|
for inp in _bsram_inputs:
|
|
add_port_wire(tt, bsram, portmap, f"{inp}{sfx}", "BSRAM_I", PinType.INPUT)
|
|
for idx in range(3):
|
|
add_port_wire(tt, bsram, portmap, f"BLKSEL{sfx}{idx}", "BSRAM_I", PinType.INPUT)
|
|
for idx in range(14):
|
|
add_port_wire(tt, bsram, portmap, f"AD{sfx}{idx}", "BSRAM_I", PinType.INPUT)
|
|
for idx in range(18):
|
|
add_port_wire(tt, bsram, portmap, f"DI{sfx}{idx}", "BSRAM_I", PinType.INPUT)
|
|
add_port_wire(tt, bsram, portmap, f"DO{sfx}{idx}", "BSRAM_O", PinType.OUTPUT)
|
|
if not sfx:
|
|
for idx in range(18, 36):
|
|
add_port_wire(tt, bsram, portmap, f"DI{idx}", "BSRAM_I", PinType.INPUT)
|
|
add_port_wire(tt, bsram, portmap, f"DO{idx}", "BSRAM_O", PinType.OUTPUT)
|
|
|
|
tdesc.tiletype = tiletype
|
|
return tt
|
|
|
|
# DSP
|
|
_mult_inputs = {'ASEL', 'BSEL', 'ASIGN', 'BSIGN'}
|
|
def create_dsp_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
|
|
typename = "DSP"
|
|
tiletype = f"{typename}_{ttyp}"
|
|
if tdesc.sfx != 0:
|
|
tiletype += f"_{tdesc.sfx}"
|
|
tt = chip.create_tile_type(tiletype)
|
|
tt.extra_data = TileExtraData(chip.strs.id(typename))
|
|
|
|
# create big DSP
|
|
belname = f'DSP'
|
|
portmap = db.grid[y][x].bels[belname].portmap
|
|
dsp = tt.create_bel(belname, "DSP", DSP_Z)
|
|
dsp.flags = BEL_FLAG_HIDDEN
|
|
|
|
# create DSP macros
|
|
for idx in range(2):
|
|
belname = f'DSP{idx}'
|
|
portmap = db.grid[y][x].bels[belname].portmap
|
|
dsp = tt.create_bel(belname, "DSP", eval(f'DSP_{idx}_Z'))
|
|
dsp.flags = BEL_FLAG_HIDDEN
|
|
|
|
# create pre-adders
|
|
for mac, idx in [(mac, idx) for mac in range(2) for idx in range(4)]:
|
|
belname = f'PADD9{mac}{idx}'
|
|
portmap = db.grid[y][x].bels[belname].portmap
|
|
dsp = tt.create_bel(belname, "PADD9", eval(f'PADD9_{mac}_{idx}_Z'))
|
|
|
|
add_port_wire(tt, dsp, portmap, "ADDSUB", "DSP_I", PinType.INPUT)
|
|
for sfx in {'A', 'B'}:
|
|
for inp in range(9):
|
|
add_port_wire(tt, dsp, portmap, f"{sfx}{inp}", "DSP_I", PinType.INPUT)
|
|
for inp in range(9):
|
|
add_port_wire(tt, dsp, portmap, f"C{inp}", "DSP_I", PinType.INPUT)
|
|
for inp in range(4):
|
|
add_port_wire(tt, dsp, portmap, f"CE{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"CLK{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"RESET{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, "ASEL", "DSP_I", PinType.INPUT)
|
|
for outp in range(9):
|
|
add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
|
|
|
|
for mac, idx in [(mac, idx) for mac in range(2) for idx in range(2)]:
|
|
belname = f'PADD18{mac}{idx}'
|
|
portmap = db.grid[y][x].bels[belname].portmap
|
|
dsp = tt.create_bel(belname, "PADD18", eval(f'PADD18_{mac}_{idx}_Z'))
|
|
|
|
add_port_wire(tt, dsp, portmap, "ADDSUB", "DSP_I", PinType.INPUT)
|
|
for sfx in {'A', 'B'}:
|
|
for inp in range(18):
|
|
add_port_wire(tt, dsp, portmap, f"{sfx}{inp}", "DSP_I", PinType.INPUT)
|
|
for inp in range(18):
|
|
add_port_wire(tt, dsp, portmap, f"C{inp}", "DSP_I", PinType.INPUT)
|
|
for inp in range(4):
|
|
add_port_wire(tt, dsp, portmap, f"CE{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"CLK{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"RESET{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, "ASEL", "DSP_I", PinType.INPUT)
|
|
for outp in range(18):
|
|
add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
|
|
|
|
# create multipliers
|
|
# mult 9x9
|
|
for mac, idx in [(mac, idx) for mac in range(2) for idx in range(4)]:
|
|
belname = f'MULT9X9{mac}{idx}'
|
|
portmap = db.grid[y][x].bels[belname].portmap
|
|
dsp = tt.create_bel(belname, "MULT9X9", eval(f'MULT9X9_{mac}_{idx}_Z'))
|
|
|
|
for sfx in {'A', 'B'}:
|
|
for inp in range(9):
|
|
add_port_wire(tt, dsp, portmap, f"{sfx}{inp}", "DSP_I", PinType.INPUT)
|
|
for inp in _mult_inputs:
|
|
add_port_wire(tt, dsp, portmap, inp, "DSP_I", PinType.INPUT)
|
|
for inp in range(4):
|
|
add_port_wire(tt, dsp, portmap, f"CE{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"CLK{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"RESET{inp}", "DSP_I", PinType.INPUT)
|
|
for outp in range(18):
|
|
add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
|
|
|
|
# mult 18x18
|
|
for mac, idx in [(mac, idx) for mac in range(2) for idx in range(2)]:
|
|
belname = f'MULT18X18{mac}{idx}'
|
|
portmap = db.grid[y][x].bels[belname].portmap
|
|
dsp = tt.create_bel(belname, "MULT18X18", eval(f'MULT18X18_{mac}_{idx}_Z'))
|
|
|
|
for sfx in {'A', 'B'}:
|
|
for inp in range(18):
|
|
add_port_wire(tt, dsp, portmap, f"{sfx}{inp}", "DSP_I", PinType.INPUT)
|
|
for inp in _mult_inputs:
|
|
add_port_wire(tt, dsp, portmap, inp, "DSP_I", PinType.INPUT)
|
|
for inp in range(4):
|
|
add_port_wire(tt, dsp, portmap, f"CE{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"CLK{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"RESET{inp}", "DSP_I", PinType.INPUT)
|
|
for outp in range(36):
|
|
add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
|
|
|
|
# mult 36x36
|
|
belname = 'MULT36X36'
|
|
portmap = db.grid[y][x].bels[belname].portmap
|
|
dsp = tt.create_bel(belname, "MULT36X36", MULT36X36_Z)
|
|
|
|
# LSB 18x18 multipliers sign ports must be zero
|
|
add_port_wire(tt, dsp, db.grid[y][x].bels['MULT18X1800'].portmap, 'ASIGN', "DSP_I", PinType.INPUT, 'ZERO_ASIGN0')
|
|
add_port_wire(tt, dsp, db.grid[y][x].bels['MULT18X1800'].portmap, 'BSIGN', "DSP_I", PinType.INPUT, 'ZERO_BSIGN0')
|
|
add_port_wire(tt, dsp, db.grid[y][x].bels['MULT18X1801'].portmap, 'BSIGN', "DSP_I", PinType.INPUT, 'ZERO_BSIGN1')
|
|
add_port_wire(tt, dsp, db.grid[y][x].bels['MULT18X1810'].portmap, 'ASIGN', "DSP_I", PinType.INPUT, 'ZERO_ASIGN1')
|
|
for i in range(2):
|
|
for sfx in {'A', 'B'}:
|
|
for inp in range(36):
|
|
add_port_wire(tt, dsp, portmap, f"{sfx}{inp}{i}", "DSP_I", PinType.INPUT)
|
|
for inp in {'ASIGN', 'BSIGN'}:
|
|
add_port_wire(tt, dsp, portmap, f"{inp}{i}", "DSP_I", PinType.INPUT)
|
|
for inp in range(4):
|
|
add_port_wire(tt, dsp, portmap, f"CE{inp}{i}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"CLK{inp}{i}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"RESET{inp}{i}", "DSP_I", PinType.INPUT)
|
|
for outp in range(72):
|
|
add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
|
|
|
|
# create alus
|
|
for mac in range(2):
|
|
belname = f'ALU54D{mac}'
|
|
portmap = db.grid[y][x].bels[belname].portmap
|
|
dsp = tt.create_bel(belname, "ALU54D", eval(f'ALU54D_{mac}_Z'))
|
|
|
|
for sfx in {'A', 'B'}:
|
|
for inp in range(54):
|
|
add_port_wire(tt, dsp, portmap, f"{sfx}{inp}", "DSP_I", PinType.INPUT)
|
|
for inp in {'ASIGN', 'BSIGN'}:
|
|
add_port_wire(tt, dsp, portmap, inp, "DSP_I", PinType.INPUT)
|
|
for inp in range(4):
|
|
add_port_wire(tt, dsp, portmap, f"CE{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"CLK{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"RESET{inp}", "DSP_I", PinType.INPUT)
|
|
if inp < 2:
|
|
add_port_wire(tt, dsp, portmap, f"ACCLOAD{inp}", "DSP_I", PinType.INPUT)
|
|
for outp in range(54):
|
|
add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
|
|
|
|
# create multalus
|
|
# MULTALU18X18
|
|
for mac in range(2):
|
|
belname = f'MULTALU18X18{mac}'
|
|
portmap = db.grid[y][x].bels[belname].portmap
|
|
dsp = tt.create_bel(belname, "MULTALU18X18", eval(f'MULTALU18X18_{mac}_Z'))
|
|
|
|
for i in range(2):
|
|
for sfx in {'ASIGN', 'BSIGN'}:
|
|
add_port_wire(tt, dsp, portmap, f"{sfx}{i}", "DSP_I", PinType.INPUT)
|
|
for sfx in {'A', 'B'}:
|
|
for inp in range(18):
|
|
add_port_wire(tt, dsp, portmap, f"{sfx}{inp}{i}", "DSP_I", PinType.INPUT)
|
|
for sfx in {'C', 'D'}:
|
|
for inp in range(54):
|
|
add_port_wire(tt, dsp, portmap, f"{sfx}{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, "DSIGN", "DSP_I", PinType.INPUT)
|
|
for inp in range(4):
|
|
add_port_wire(tt, dsp, portmap, f"CE{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"CLK{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"RESET{inp}", "DSP_I", PinType.INPUT)
|
|
if inp < 2:
|
|
add_port_wire(tt, dsp, portmap, f"ACCLOAD{inp}", "DSP_I", PinType.INPUT)
|
|
for outp in range(54):
|
|
add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
|
|
|
|
# MULTALU36X18
|
|
for mac in range(2):
|
|
belname = f'MULTALU36X18{mac}'
|
|
portmap = db.grid[y][x].bels[belname].portmap
|
|
dsp = tt.create_bel(belname, "MULTALU36X18", eval(f'MULTALU36X18_{mac}_Z'))
|
|
|
|
for i in range(2):
|
|
for sfx in {'ASIGN', 'BSIGN'}:
|
|
add_port_wire(tt, dsp, portmap, f"{sfx}{i}", "DSP_I", PinType.INPUT)
|
|
for inp in range(18):
|
|
add_port_wire(tt, dsp, portmap, f"A{inp}{i}", "DSP_I", PinType.INPUT)
|
|
for inp in range(7):
|
|
add_port_wire(tt, dsp, portmap, f"ALUSEL{inp}", "DSP_I", PinType.INPUT)
|
|
for inp in range(36):
|
|
add_port_wire(tt, dsp, portmap, f"B{inp}", "DSP_I", PinType.INPUT)
|
|
for inp in range(54):
|
|
add_port_wire(tt, dsp, portmap, f"C{inp}", "DSP_I", PinType.INPUT)
|
|
for inp in range(4):
|
|
add_port_wire(tt, dsp, portmap, f"CE{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"CLK{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"RESET{inp}", "DSP_I", PinType.INPUT)
|
|
for outp in range(54):
|
|
add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
|
|
|
|
# MULTADDALU18X18
|
|
for mac in range(2):
|
|
belname = f'MULTADDALU18X18{mac}'
|
|
portmap = db.grid[y][x].bels[belname].portmap
|
|
dsp = tt.create_bel(belname, "MULTADDALU18X18", eval(f'MULTADDALU18X18_{mac}_Z'))
|
|
|
|
for i in range(2):
|
|
for sfx in {'ASIGN', 'BSIGN', 'ASEL', 'BSEL'}:
|
|
add_port_wire(tt, dsp, portmap, f"{sfx}{i}", "DSP_I", PinType.INPUT)
|
|
for inp in range(18):
|
|
add_port_wire(tt, dsp, portmap, f"A{inp}{i}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"B{inp}{i}", "DSP_I", PinType.INPUT)
|
|
for inp in range(7):
|
|
add_port_wire(tt, dsp, portmap, f"ALUSEL{inp}", "DSP_I", PinType.INPUT)
|
|
for inp in range(54):
|
|
add_port_wire(tt, dsp, portmap, f"C{inp}", "DSP_I", PinType.INPUT)
|
|
for inp in range(4):
|
|
add_port_wire(tt, dsp, portmap, f"CE{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"CLK{inp}", "DSP_I", PinType.INPUT)
|
|
add_port_wire(tt, dsp, portmap, f"RESET{inp}", "DSP_I", PinType.INPUT)
|
|
for outp in range(54):
|
|
add_port_wire(tt, dsp, portmap, f"DOUT{outp}", "DSP_O", PinType.OUTPUT)
|
|
|
|
tdesc.tiletype = tiletype
|
|
return tt
|
|
|
|
# PLL main tile
|
|
_pll_inputs = {'CLKFB', 'FBDSEL0', 'FBDSEL1', 'FBDSEL2', 'FBDSEL3',
|
|
'FBDSEL4', 'FBDSEL5', 'IDSEL0', 'IDSEL1', 'IDSEL2', 'IDSEL3',
|
|
'IDSEL4', 'IDSEL5', 'ODSEL0', 'ODSEL1', 'ODSEL2', 'ODSEL3',
|
|
'ODSEL4', 'ODSEL5', 'RESET', 'RESET_P', 'PSDA0', 'PSDA1',
|
|
'PSDA2', 'PSDA3', 'DUTYDA0', 'DUTYDA1', 'DUTYDA2', 'DUTYDA3',
|
|
'FDLY0', 'FDLY1', 'FDLY2', 'FDLY3', 'CLKIN', 'VREN'}
|
|
_pll_outputs = {'CLKOUT', 'LOCK', 'CLKOUTP', 'CLKOUTD', 'CLKOUTD3'}
|
|
def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc: TypeDesc):
|
|
typename = "PLL"
|
|
tiletype = f"{typename}_{ttyp}"
|
|
if tdesc.sfx != 0:
|
|
tiletype += f"_{tdesc.sfx}"
|
|
|
|
# disabled PLLs
|
|
if tdesc.extra_func and 'disabled' in tdesc.extra_func and 'PLL' in tdesc.extra_func['disabled']:
|
|
tiletype += '_disabled'
|
|
tt = chip.create_tile_type(tiletype)
|
|
tt.extra_data = TileExtraData(chip.strs.id(typename))
|
|
tdesc.tiletype = tiletype
|
|
return tt
|
|
tt = chip.create_tile_type(tiletype)
|
|
tt.extra_data = TileExtraData(chip.strs.id(typename))
|
|
|
|
|
|
# wires
|
|
if chip.name == 'GW1NS-4':
|
|
pll_name = 'PLLVR'
|
|
bel_type = 'PLLVR'
|
|
else:
|
|
pll_name = 'RPLLA'
|
|
bel_type = 'rPLL'
|
|
portmap = db.grid[y][x].bels[pll_name].portmap
|
|
pll = tt.create_bel("PLL", bel_type, z = PLL_Z)
|
|
pll.flags = BEL_FLAG_GLOBAL
|
|
for pin, wire in portmap.items():
|
|
if pin in _pll_inputs:
|
|
tt.create_wire(wire, "PLL_I")
|
|
tt.add_bel_pin(pll, pin, wire, PinType.INPUT)
|
|
else:
|
|
assert pin in _pll_outputs, f"Unknown PLL pin {pin}"
|
|
tt.create_wire(wire, "PLL_O")
|
|
tt.add_bel_pin(pll, pin, wire, PinType.OUTPUT)
|
|
tdesc.tiletype = tiletype
|
|
return tt
|
|
|
|
# add Pll's bel to the pad
|
|
def add_pll(chip: Chip, db: chipdb, pad: PadInfo, ioloc: str):
|
|
try:
|
|
if ioloc in db.pad_pll:
|
|
row, col, ttyp, bel_name = db.pad_pll[ioloc]
|
|
pad.extra_data = PadExtraData(chip.strs.id(f'X{col}Y{row}'), chip.strs.id(bel_name), chip.strs.id(ttyp))
|
|
except:
|
|
return
|
|
|
|
# pinouts, packages...
|
|
_tbrlre = re.compile(r"IO([TBRL])(\d+)(\w)")
|
|
def create_packages(chip: Chip, db: chipdb):
|
|
def ioloc_to_tile_bel(ioloc):
|
|
side, num, bel_idx = _tbrlre.match(ioloc).groups()
|
|
if side == 'T':
|
|
row = 0
|
|
col = int(num) - 1
|
|
elif side == 'B':
|
|
row = db.rows - 1
|
|
col = int(num) - 1
|
|
elif side == 'L':
|
|
row = int(num) - 1
|
|
col = 0
|
|
elif side == 'R':
|
|
row = int(num) - 1
|
|
col = db.cols - 1
|
|
return (f'X{col}Y{row}', f'IOB{bel_idx}')
|
|
|
|
created_pkgs = set()
|
|
for partno_spd, partdata in db.packages.items():
|
|
pkgname, variant, spd = partdata
|
|
partno = partno_spd.removesuffix(spd) # drop SPEED like 'C7/I6'
|
|
if partno in created_pkgs:
|
|
continue
|
|
created_pkgs.add(partno)
|
|
pkg = chip.create_package(partno)
|
|
for pinno, pininfo in db.pinout[variant][pkgname].items():
|
|
io_loc, cfgs = pininfo
|
|
tile, bel = ioloc_to_tile_bel(io_loc)
|
|
pad_func = ""
|
|
for cfg in cfgs:
|
|
pad_func += cfg + "/"
|
|
pad_func = pad_func.rstrip('/')
|
|
bank = int(db.pin_bank[io_loc])
|
|
pad = pkg.create_pad(pinno, tile, bel, pad_func, bank)
|
|
# add PLL if any is connected
|
|
add_pll(chip, db, pad, io_loc)
|
|
|
|
# Extra chip data
|
|
def create_extra_data(chip: Chip, db: chipdb, chip_flags: int):
|
|
chip.extra_data = ChipExtraData(chip.strs, chip_flags, None)
|
|
chip.extra_data.create_bottom_io()
|
|
for net_a, net_b in db.bottom_io[2]:
|
|
chip.extra_data.add_bottom_io_cnd(net_a, net_b)
|
|
for diff_type in db.diff_io_types:
|
|
chip.extra_data.add_diff_io_type(diff_type)
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(description='Make Gowin BBA')
|
|
parser.add_argument('-d', '--device', required=True)
|
|
parser.add_argument('-o', '--output', default="out.bba")
|
|
|
|
args = parser.parse_args()
|
|
|
|
device = args.device
|
|
with gzip.open(importlib.resources.files("apycula").joinpath(f"{device}.pickle"), 'rb') as f:
|
|
db = pickle.load(f)
|
|
|
|
chip_flags = 0;
|
|
if device not in {"GW1NS-4", "GW1N-9"}:
|
|
chip_flags &= CHIP_HAS_SP32;
|
|
|
|
X = db.cols;
|
|
Y = db.rows;
|
|
|
|
ch = Chip("gowin", device, X, Y)
|
|
|
|
# Init constant ids
|
|
ch.strs.read_constids(path.join(path.dirname(__file__), "constids.inc"))
|
|
|
|
# packages from parntnumbers
|
|
create_packages(ch, db)
|
|
|
|
# The manufacturer distinguishes by externally identical tiles, so keep
|
|
# these differences (in case it turns out later that there is a slightly
|
|
# different routing or something like that).
|
|
logic_tiletypes = db.tile_types['C']
|
|
io_tiletypes = db.tile_types['I']
|
|
ssram_tiletypes = db.tile_types['M']
|
|
pll_tiletypes = db.tile_types['P']
|
|
bsram_tiletypes = db.tile_types.get('B', set())
|
|
dsp_tiletypes = db.tile_types.get('D', set())
|
|
|
|
# Setup tile grid
|
|
for x in range(X):
|
|
for y in range(Y):
|
|
ttyp = db.grid[y][x].ttyp
|
|
if (x == 0 or x == X - 1) and (y == 0 or y == Y - 1):
|
|
assert ttyp not in created_tiletypes, "Duplication of corner types"
|
|
create_tiletype(create_corner_tiletype, ch, db, x, y, ttyp)
|
|
continue
|
|
elif ttyp in logic_tiletypes:
|
|
create_tiletype(create_logic_tiletype, ch, db, x, y, ttyp)
|
|
elif ttyp in ssram_tiletypes:
|
|
create_tiletype(create_ssram_tiletype, ch, db, x, y, ttyp)
|
|
elif ttyp in io_tiletypes:
|
|
create_tiletype(create_io_tiletype, ch, db, x, y, ttyp)
|
|
elif ttyp in pll_tiletypes:
|
|
create_tiletype(create_pll_tiletype, ch, db, x, y, ttyp)
|
|
elif ttyp in bsram_tiletypes:
|
|
create_tiletype(create_bsram_tiletype, ch, db, x, y, ttyp)
|
|
elif ttyp in dsp_tiletypes:
|
|
create_tiletype(create_dsp_tiletype, ch, db, x, y, ttyp)
|
|
else:
|
|
create_tiletype(create_null_tiletype, ch, db, x, y, ttyp)
|
|
|
|
# Create nodes between tiles
|
|
create_nodes(ch, db)
|
|
create_extra_data(ch, db, chip_flags)
|
|
ch.write_bba(args.output)
|
|
if __name__ == '__main__':
|
|
main()
|