nextpnr/himbaechel/uarch/gowin
YRabbit 4e8436a1fc gowin: Himbaechel. Allow to combine IOLOGIC.
Corrects the situation when it is impossible to use IOBUF with two
IOLOGIC elements at the same time - input and output.

Addresses https://github.com/YosysHQ/nextpnr/issues/1275

This is done by dividing one IOLOGIC Bel into two - input IOLOGIC and
output IOLOGIC plus checking for compatibility of the cells located
there.

At the moment, this check is simple and allows only the combination of
DDR and DDRC primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-03-13 14:22:43 +01:00
..
CMakeLists.txt gowin: Himbaechel. Add GW1NZ-1 BSRAM. 2023-11-26 13:08:09 +01:00
constids.inc gowin: Himbaechel. Allow to combine IOLOGIC. 2024-03-13 14:22:43 +01:00
cst.cc gowin: Himbaechel. Extend clock router 2023-09-08 09:15:35 +02:00
cst.h gowin: Himbaechel. Add constraint file processing. 2023-08-31 08:28:09 +02:00
globals.cc gowin: Himbaechel. Improve the global router 2024-03-13 14:22:11 +01:00
globals.h gowin: Himbaechel. Add a clock router. 2023-08-31 08:28:09 +02:00
gowin_arch_gen.py gowin: Himbaechel. Allow to combine IOLOGIC. 2024-03-13 14:22:43 +01:00
gowin_utils.cc gowin: Himbaechel. Allow to combine IOLOGIC. 2024-03-13 14:22:43 +01:00
gowin_utils.h gowin: Himbaechel. Deal with SP BSRAM ports. 2024-01-23 14:00:29 +01:00
gowin.cc gowin: Himbaechel. Allow to combine IOLOGIC. 2024-03-13 14:22:43 +01:00
gowin.h gowin: Himbaechel. Allow to combine IOLOGIC. 2024-03-13 14:22:43 +01:00
pack.cc gowin: Himbaechel. Allow to combine IOLOGIC. 2024-03-13 14:22:43 +01:00
pack.h gowin: Himbaechel. Add ALU. 2023-08-31 08:28:09 +02:00