590b9050ff
A simple router that takes advantage of the fact that in each cell with DFFs their CLK inputs can directly connect to the global clock network. Networks with a large number of such sinks are sought and then each network is assigned to the available independent global clock networks. There are limited possibilities for routing mixed networks, that is, when the sinks are not only CLKs: in this case an attempt is made to use wires such as SN10/20 and EW10/20, that is, one short transition can be added between the global clock network and the sink. * At this time, networks with a source other than the I/O pin are not supported. This is typical for Tangnano4k and runber boards. * Router is disabled by default, you need to specify option --enable-globals to activate * No new chip bases are required. This may change in the distant future. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
336 lines
13 KiB
C++
336 lines
13 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "globals.h"
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#include <algorithm>
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#include <iomanip>
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#include <iostream>
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#include <queue>
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#include "cells.h"
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#include "log.h"
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#include "nextpnr.h"
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#include "place_common.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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class GowinGlobalRouter
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{
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public:
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GowinGlobalRouter(Context *ctx) : ctx(ctx){};
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private:
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// wire -> clock#
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dict<WireId, int> used_wires;
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// ordered nets
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struct onet_t
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{
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IdString name;
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int clock_ports;
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WireId clock_io_wire; // IO wire if there is one
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onet_t() : name(IdString()), clock_ports(0), clock_io_wire(WireId()) {}
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onet_t(IdString _name) : name(_name), clock_ports(0), clock_io_wire(WireId()) {}
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// sort
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bool operator<(const onet_t &other) const
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{
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if ((clock_io_wire != WireId()) ^ (other.clock_io_wire != WireId())) {
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return !(clock_io_wire != WireId());
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}
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return clock_ports < other.clock_ports;
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}
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// search
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bool operator==(const onet_t &other) const { return name == other.name; }
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};
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bool is_clock_port(PortRef const &user)
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{
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if (user.cell->type == id_SLICE && user.port == id_CLK) {
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return true;
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}
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return false;
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}
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WireId clock_io(PortRef const &driver)
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{
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// XXX normally all alternative functions of the pins should be passed
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// in the chip database, but at the moment we find them from aliases/pips
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// XXX check diff inputs too
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if (driver.cell == nullptr || driver.cell->bel == BelId()) {
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return WireId();
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}
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// clock IOs have pips output->SPINExx
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BelInfo &bel = ctx->bels.at(driver.cell->bel);
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if (bel.type != id_IOB) {
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return WireId();
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}
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WireId wire = bel.pins[id_O].wire;
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for (auto const &pip : ctx->getPipsDownhill(wire)) {
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if (ctx->wire_info(ctx->getPipDstWire(pip)).type.str(ctx).rfind("SPINE", 0) == 0) {
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return wire;
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}
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}
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return WireId();
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}
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// gather the clock nets
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void gather_clock_nets(std::vector<onet_t> &clock_nets)
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{
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for (auto const &net : ctx->nets) {
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NetInfo const *ni = net.second.get();
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auto new_clock = clock_nets.end();
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WireId clock_wire = clock_io(ni->driver);
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if (clock_wire != WireId()) {
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clock_nets.emplace_back(net.first);
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new_clock = --clock_nets.end();
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new_clock->clock_io_wire = clock_wire;
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}
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for (auto const &user : ni->users) {
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if (is_clock_port(user)) {
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if (new_clock == clock_nets.end()) {
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clock_nets.emplace_back(net.first);
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new_clock = --clock_nets.end();
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}
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++(new_clock->clock_ports);
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}
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}
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}
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// need to prioritize the nets
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std::sort(clock_nets.begin(), clock_nets.end());
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if (ctx->verbose) {
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for (auto const &net : clock_nets) {
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log_info(" Net:%s, ports:%d, io:%s\n", net.name.c_str(ctx), net.clock_ports,
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net.clock_io_wire == WireId() ? "No" : net.clock_io_wire.c_str(ctx));
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}
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}
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}
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// non clock port
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// returns GB pip
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IdString route_to_non_clock_port(WireId const dstWire, int clock, pool<IdString> &used_pips,
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pool<IdString> &undo_wires)
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{
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static std::vector<IdString> one_hop = {id_S111, id_S121, id_N111, id_N121, id_W111, id_W121, id_E111, id_E121};
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char buf[40];
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// uphill pips
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for (auto const &uphill : ctx->getPipsUphill(dstWire)) {
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WireId srcWire = ctx->getPipSrcWire(uphill);
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if (find(one_hop.begin(), one_hop.end(), ctx->wire_info(ctx->getPipSrcWire(uphill)).type) !=
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one_hop.end()) {
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// found one hop pip
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if (used_wires.count(srcWire)) {
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if (used_wires[srcWire] != clock) {
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continue;
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}
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}
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WireInfo wi = ctx->wire_info(srcWire);
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std::string wire_alias = srcWire.str(ctx).substr(srcWire.str(ctx).rfind("_") + 1);
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snprintf(buf, sizeof(buf), "R%dC%d_GB%d0_%s", wi.y + 1, wi.x + 1, clock, wire_alias.c_str());
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IdString gb = ctx->id(buf);
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auto up_pips = ctx->getPipsUphill(srcWire);
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if (find(up_pips.begin(), up_pips.end(), gb) != up_pips.end()) {
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if (!used_wires.count(srcWire)) {
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used_wires.insert(std::make_pair(srcWire, clock));
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undo_wires.insert(srcWire);
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}
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used_pips.insert(uphill);
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if (ctx->verbose) {
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log_info(" 1-hop Pip:%s\n", uphill.c_str(ctx));
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}
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return gb;
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}
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}
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}
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return IdString();
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}
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// route one net
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void route_net(onet_t const &net, int clock)
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{
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// For failed routing undo
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pool<IdString> used_pips;
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pool<IdString> undo_wires;
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log_info(" Route net %s, use clock #%d.\n", net.name.c_str(ctx), clock);
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for (auto const &user : ctx->net_info(net.name).users) {
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// >>> port <- GB<clock>0
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WireId dstWire = ctx->getNetinfoSinkWire(&ctx->net_info(net.name), user, 0);
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if (ctx->verbose) {
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log_info(" Cell:%s, port:%s, wire:%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx),
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dstWire.c_str(ctx));
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}
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char buf[30];
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PipId gb_pip_id;
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if (user.port == id_CLK) {
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WireInfo const wi = ctx->wire_info(dstWire);
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snprintf(buf, sizeof(buf), "R%dC%d_GB%d0_%s", wi.y + 1, wi.x + 1, clock,
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ctx->wire_info(dstWire).type.c_str(ctx));
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gb_pip_id = ctx->id(buf);
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// sanity
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NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), gb_pip_id) !=
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ctx->getPipsUphill(dstWire).end());
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} else {
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// Non clock port
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gb_pip_id = route_to_non_clock_port(dstWire, clock, used_pips, undo_wires);
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if (gb_pip_id == IdString()) {
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if (ctx->verbose) {
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log_info(" Can't find route to %s, net %s will be routed in a standard way.\n",
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dstWire.c_str(ctx), net.name.c_str(ctx));
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}
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for (IdString const &undo : undo_wires) {
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used_wires.erase(undo);
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}
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return;
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}
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}
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if (ctx->verbose) {
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log_info(" GB Pip:%s\n", gb_pip_id.c_str(ctx));
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}
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if (used_pips.count(gb_pip_id)) {
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if (ctx->verbose) {
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log_info(" ^routed already^\n");
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}
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continue;
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}
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used_pips.insert(gb_pip_id);
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// >>> GBOx <- GTx0
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dstWire = ctx->getPipSrcWire(gb_pip_id);
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WireInfo dstWireInfo = ctx->wire_info(dstWire);
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int branch_tap_idx = clock > 3 ? 1 : 0;
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snprintf(buf, sizeof(buf), "R%dC%d_GT%d0_GBO%d", dstWireInfo.y + 1, dstWireInfo.x + 1, branch_tap_idx,
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branch_tap_idx);
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PipId gt_pip_id = ctx->id(buf);
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if (ctx->verbose) {
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log_info(" GT Pip:%s\n", buf);
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}
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// sanity
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NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), gt_pip_id) !=
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ctx->getPipsUphill(dstWire).end());
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// if already routed
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if (used_pips.count(gt_pip_id)) {
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if (ctx->verbose) {
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log_info(" ^routed already^\n");
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}
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continue;
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}
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used_pips.insert(gt_pip_id);
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// >>> GTx0 <- SPINExx
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// XXX no optimization here, we need to store
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// the SPINE <-> clock# correspondence in the database. In the
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// meantime, we define in run-time in a completely suboptimal way.
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std::vector<std::string> clock_spine;
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dstWire = ctx->getPipSrcWire(gt_pip_id);
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for (auto const &uphill_pip : ctx->getPipsUphill(dstWire)) {
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std::string name = ctx->wire_info(ctx->getPipSrcWire(uphill_pip)).type.str(ctx);
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if (name.rfind("SPINE", 0) == 0) {
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clock_spine.push_back(name);
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}
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}
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sort(clock_spine.begin(), clock_spine.end(), [](const std::string &a, const std::string &b) -> bool {
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return (a.size() < b.size()) || (a.size() == b.size() && a < b);
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});
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dstWireInfo = ctx->wire_info(dstWire);
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snprintf(buf, sizeof(buf), "R%dC%d_%s_GT%d0", dstWireInfo.y + 1, dstWireInfo.x + 1,
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clock_spine[clock - branch_tap_idx * 4].c_str(), branch_tap_idx);
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PipId spine_pip_id = ctx->id(buf);
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if (ctx->verbose) {
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log_info(" Spine Pip:%s\n", buf);
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}
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// sanity
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NPNR_ASSERT(find(ctx->getPipsUphill(dstWire).begin(), ctx->getPipsUphill(dstWire).end(), spine_pip_id) !=
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ctx->getPipsUphill(dstWire).end());
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// if already routed
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if (used_pips.count(spine_pip_id)) {
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if (ctx->verbose) {
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log_info(" ^routed already^\n");
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}
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continue;
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}
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used_pips.insert(spine_pip_id);
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// >>> SPINExx <- IO
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dstWire = ctx->getPipSrcWire(spine_pip_id);
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dstWireInfo = ctx->wire_info(dstWire);
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PipId io_pip_id = PipId();
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for (auto const &uphill_pip : ctx->getPipsUphill(dstWire)) {
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if (ctx->getPipSrcWire(uphill_pip) == net.clock_io_wire) {
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io_pip_id = uphill_pip;
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}
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}
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NPNR_ASSERT(io_pip_id != PipId());
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if (ctx->verbose) {
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log_info(" IO Pip:%s\n", io_pip_id.c_str(ctx));
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}
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// if already routed
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if (used_pips.count(io_pip_id)) {
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if (ctx->verbose) {
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log_info(" ^routed already^\n");
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}
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continue;
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}
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used_pips.insert(io_pip_id);
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}
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log_info(" Net %s is routed.\n", net.name.c_str(ctx));
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for (auto const pip : used_pips) {
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ctx->bindPip(pip, &ctx->net_info(net.name), STRENGTH_LOCKED);
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}
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ctx->bindWire(net.clock_io_wire, &ctx->net_info(net.name), STRENGTH_LOCKED);
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}
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public:
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Context *ctx;
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void route_globals()
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{
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log_info("Routing globals...\n");
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std::vector<onet_t> clock_nets;
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gather_clock_nets(clock_nets);
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// XXX we need to use the list of indexes of clocks from the database
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// use 6 clocks (XXX 3 for GW1NZ-1)
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int max_clock = 3, cur_clock = -1;
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for (auto const &net : clock_nets) {
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// XXX only IO clock for now
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if (net.clock_io_wire == WireId()) {
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log_info(" Non IO clock, skip %s.\n", net.name.c_str(ctx));
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continue;
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}
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if (++cur_clock >= max_clock) {
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log_info(" No more clock wires left, skip the remaining nets.\n");
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break;
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}
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route_net(net, cur_clock);
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}
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}
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};
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void route_gowin_globals(Context *ctx)
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{
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GowinGlobalRouter router(ctx);
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router.route_globals();
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}
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NEXTPNR_NAMESPACE_END
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