170 lines
3.7 KiB
Verilog
170 lines
3.7 KiB
Verilog
module io_wrapper(input clk_pin, cen_pin, rst_pin, ina_pin, inb_pin,
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output outa_pin, outb_pin, outc_pin, outd_pin);
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wire clk, cen, rst, ina, inb, outa, outb, outc, outd;
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(* BEL="0_14_io1" *)
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SB_IO #(
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.PIN_TYPE(6'b 0000_01),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0)
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) clk_iob (
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.PACKAGE_PIN(clk_pin),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(),
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.D_OUT_1(),
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.D_IN_0(clk),
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.D_IN_1()
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);
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(* BEL="0_14_io0" *)
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SB_IO #(
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.PIN_TYPE(6'b 0000_01),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0)
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) cen_iob (
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.PACKAGE_PIN(cen_pin),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(),
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.D_OUT_1(),
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.D_IN_0(cen),
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.D_IN_1()
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);
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(* BEL="0_13_io1" *)
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SB_IO #(
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.PIN_TYPE(6'b 0000_01),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0)
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) rst_iob (
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.PACKAGE_PIN(rst_pin),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(),
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.D_OUT_1(),
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.D_IN_0(rst),
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.D_IN_1()
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);
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(* BEL="0_13_io0" *)
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SB_IO #(
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.PIN_TYPE(6'b 0000_01),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0)
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) ina_iob (
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.PACKAGE_PIN(ina_pin),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(),
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.D_OUT_1(),
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.D_IN_0(ina),
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.D_IN_1()
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);
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(* BEL="0_12_io1" *)
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SB_IO #(
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.PIN_TYPE(6'b 0000_01),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0)
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) inb_iob (
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.PACKAGE_PIN(inb_pin),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(),
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.D_OUT_1(),
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.D_IN_0(inb),
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.D_IN_1()
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);
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(* BEL="0_12_io0" *)
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SB_IO #(
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.PIN_TYPE(6'b 0110_01),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0)
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) outa_iob (
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.PACKAGE_PIN(outa_pin),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(outa),
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.D_OUT_1(),
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.D_IN_0(),
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.D_IN_1()
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);
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(* BEL="0_11_io1" *)
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SB_IO #(
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.PIN_TYPE(6'b 0110_01),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0)
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) outb_iob (
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.PACKAGE_PIN(outb_pin),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(outb),
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.D_OUT_1(),
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.D_IN_0(),
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.D_IN_1()
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);
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(* BEL="0_11_io0" *)
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SB_IO #(
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.PIN_TYPE(6'b 0110_01),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0)
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) outc_iob (
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.PACKAGE_PIN(outc_pin),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(outc),
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.D_OUT_1(),
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.D_IN_0(),
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.D_IN_1()
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);
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(* BEL="0_10_io1" *)
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SB_IO #(
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.PIN_TYPE(6'b 0110_01),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0)
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) outd_iob (
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.PACKAGE_PIN(outa_pin),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(outd),
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.D_OUT_1(),
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.D_IN_0(),
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.D_IN_1()
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);
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top top_i(.clk(clk), .rst(rst), .cen(cen), .ina(ina), .inb(inb), .outa(outa), .outb(outb), .outc(outc), .outd(outd));
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endmodule
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