1124 lines
37 KiB
C++
1124 lines
37 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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* Copyright (C) 2018 Serge Bazanski <q3k@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <algorithm>
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#include <cmath>
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#include "cells.h"
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#include "gfx.h"
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#include "log.h"
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#include "nextpnr.h"
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#include "placer1.h"
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#include "router1.h"
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#include "util.h"
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#include <boost/serialization/unique_ptr.hpp>
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#include <boost/serialization/vector.hpp>
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#include <boost/serialization/unordered_map.hpp>
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#include <boost/archive/binary_iarchive.hpp>
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#include <boost/archive/binary_oarchive.hpp>
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#include <boost/iostreams/filter/zlib.hpp>
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#include <boost/iostreams/filtering_streambuf.hpp>
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struct nextpnr_binary_iarchive : public boost::archive::binary_iarchive {
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nextpnr_binary_iarchive(boost::iostreams::filtering_istreambuf &ifs, NEXTPNR_NAMESPACE::BaseCtx* ctx, const std::string& inDeviceName, const std::string& inPackageName) : boost::archive::binary_iarchive(ifs), ctx(ctx), inDeviceName(inDeviceName), inPackageName(inPackageName) {}
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NEXTPNR_NAMESPACE::BaseCtx *ctx;
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std::string inDeviceName, inPackageName;
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};
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struct nextpnr_binary_oarchive : public boost::archive::binary_oarchive {
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nextpnr_binary_oarchive(boost::iostreams::filtering_ostreambuf &ofs, NEXTPNR_NAMESPACE::BaseCtx* ctx) : boost::archive::binary_oarchive(ofs), ctx(ctx) {}
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NEXTPNR_NAMESPACE::BaseCtx *ctx;
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};
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#include "torc/common/DirectoryTree.hpp"
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//#define TORC_INFO_DB "torc_info.ar"
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NEXTPNR_NAMESPACE_BEGIN
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std::unique_ptr<const TorcInfo> torc_info;
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TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::string &inPackageName)
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: TorcInfo(inDeviceName, inPackageName)
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{
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static const boost::regex re_loc(".+_X(\\d+)Y(\\d+)");
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boost::cmatch what;
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bel_to_site_index.reserve(sites.getSiteCount() * 4);
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bel_to_loc.reserve(sites.getSiteCount() * 4);
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site_index_to_bel.resize(sites.getSiteCount());
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site_index_to_type.resize(sites.getSiteCount());
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BelId b;
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b.index = 0;
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for (SiteIndex i(0); i < sites.getSiteCount(); ++i) {
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const auto &site = sites.getSite(i);
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const auto &pd = site.getPrimitiveDefPtr();
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const auto &type = pd->getName();
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const auto &tileInfo = tiles.getTileInfo(site.getTileIndex());
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if (!boost::regex_match(tileInfo.getName(), what, re_loc))
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throw;
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const auto x = boost::lexical_cast<int>(what.str(1));
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const auto y = boost::lexical_cast<int>(what.str(2));
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if (type == "SLICEL" || type == "SLICEM") {
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bel_to_site_index.push_back(i);
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bel_to_site_index.push_back(i);
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bel_to_site_index.push_back(i);
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bel_to_site_index.push_back(i);
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site_index_to_type[i] = id_SLICE_LUT6;
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const auto site_name = site.getName();
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if (!boost::regex_match(site_name.c_str(), what, re_loc))
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throw;
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const auto sx = boost::lexical_cast<int>(what.str(1));
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if ((sx & 1) == 0) {
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bel_to_loc.emplace_back(x, y, 0);
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bel_to_loc.emplace_back(x, y, 1);
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bel_to_loc.emplace_back(x, y, 2);
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bel_to_loc.emplace_back(x, y, 3);
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} else {
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bel_to_loc.emplace_back(x, y, 4);
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bel_to_loc.emplace_back(x, y, 5);
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bel_to_loc.emplace_back(x, y, 6);
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bel_to_loc.emplace_back(x, y, 7);
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}
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site_index_to_bel[i] = b;
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b.index += 4;
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} else if (type == "IOB33S" || type == "IOB33M") {
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bel_to_site_index.push_back(i);
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site_index_to_type[i] = id_IOB33;
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bel_to_loc.emplace_back(x, y, 0);
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site_index_to_bel[i] = b;
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++b.index;
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} else {
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bel_to_site_index.push_back(i);
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site_index_to_type[i] = ctx->id(type);
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bel_to_loc.emplace_back(x, y, 0);
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site_index_to_bel[i] = b;
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++b.index;
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}
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}
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num_bels = bel_to_site_index.size();
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bel_to_site_index.shrink_to_fit();
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bel_to_loc.shrink_to_fit();
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const boost::regex re_124("(.+_)?[NESW][NESWLR](\\d)((BEG(_[NS])?)|(END(_[NS])?)|[A-E])?\\d(_\\d)?");
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const boost::regex re_L("(.+_)?L(H|V|VB)(_L)?\\d+(_\\d)?");
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const boost::regex re_BYP("BYP(_ALT)?\\d");
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const boost::regex re_BYP_B("BYP_[BL]\\d");
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const boost::regex re_BOUNCE_NS("(BYP|FAN)_BOUNCE_[NS]3_\\d");
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const boost::regex re_FAN("FAN(_ALT)?\\d");
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const boost::regex re_CLB_I1_6("CLBL[LM]_(L|LL|M)_[A-D]([1-6])");
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const boost::regex bufg_i("(CMT|CLK)_BUFG_BUFGCTRL\\d+_I0");
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const boost::regex bufg_o("(CMT|CLK)_BUFG_BUFGCTRL\\d+_O");
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const boost::regex int_clk("CLK(_L)?[01]");
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const boost::regex gclk("GCLK_(L_)?B\\d+(_EAST|_WEST)?");
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std::unordered_map</*TileTypeIndex*/ unsigned, std::vector<delay_t>> delay_lookup;
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Tilewire currentTilewire;
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WireId w;
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w.index = 0;
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for (TileIndex tileIndex(0); tileIndex < tiles.getTileCount(); tileIndex++) {
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// iterate over every wire in the tile
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const auto &tileInfo = tiles.getTileInfo(tileIndex);
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auto tileTypeIndex = tileInfo.getTypeIndex();
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auto wireCount = tiles.getWireCount(tileTypeIndex);
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currentTilewire.setTileIndex(tileIndex);
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for (WireIndex wireIndex(0); wireIndex < wireCount; wireIndex++) {
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currentTilewire.setWireIndex(wireIndex);
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const auto ¤tSegment = segments.getTilewireSegment(currentTilewire);
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if (!currentSegment.isTrivial()) {
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if (currentSegment.getAnchorTileIndex() != tileIndex)
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continue;
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segment_to_wire.emplace(currentSegment, w);
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} else
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trivial_to_wire.emplace(currentTilewire, w);
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wire_to_tilewire.push_back(currentTilewire);
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auto it = delay_lookup.find(tileTypeIndex);
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if (it == delay_lookup.end()) {
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auto wireCount = tiles.getWireCount(tileTypeIndex);
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std::vector<delay_t> tile_delays(wireCount);
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for (WireIndex wireIndex(0); wireIndex < wireCount; wireIndex++) {
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const WireInfo &wireInfo = tiles.getWireInfo(tileTypeIndex, wireIndex);
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auto wire_name = wireInfo.getName();
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if (boost::regex_match(wire_name, what, re_124)) {
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switch (what.str(2)[0]) {
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case '1':
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tile_delays[wireIndex] = 150;
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break;
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case '2':
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tile_delays[wireIndex] = 170;
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break;
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case '4':
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tile_delays[wireIndex] = 210;
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break;
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case '6':
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tile_delays[wireIndex] = 210;
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break;
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default:
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throw;
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}
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} else if (boost::regex_match(wire_name, what, re_L)) {
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std::string l(what[2]);
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if (l == "H")
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tile_delays[wireIndex] = 360;
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else if (l == "VB")
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tile_delays[wireIndex] = 300;
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else if (l == "V")
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tile_delays[wireIndex] = 350;
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else
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throw;
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} else if (boost::regex_match(wire_name, what, re_BYP)) {
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tile_delays[wireIndex] = 190;
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} else if (boost::regex_match(wire_name, what, re_BYP_B)) {
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} else if (boost::regex_match(wire_name, what, re_FAN)) {
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tile_delays[wireIndex] = 190;
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} else if (boost::regex_match(wire_name, what, re_CLB_I1_6)) {
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switch (what.str(2)[0]) {
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case '1':
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tile_delays[wireIndex] = 280;
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break;
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case '2':
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tile_delays[wireIndex] = 280;
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break;
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case '3':
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tile_delays[wireIndex] = 180;
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break;
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case '4':
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tile_delays[wireIndex] = 180;
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break;
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case '5':
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tile_delays[wireIndex] = 80;
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break;
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case '6':
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tile_delays[wireIndex] = 40;
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break;
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default:
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throw;
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}
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}
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}
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it = delay_lookup.emplace(tileTypeIndex, std::move(tile_delays)).first;
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}
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assert(it != delay_lookup.end());
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DelayInfo d;
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d.delay = it->second[currentTilewire.getWireIndex()];
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wire_to_delay.emplace_back(std::move(d));
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++w.index;
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}
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}
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wire_to_tilewire.shrink_to_fit();
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wire_to_delay.shrink_to_fit();
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num_wires = wire_to_tilewire.size();
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wire_to_pips_downhill.resize(num_wires);
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// std::unordered_map<Arc, int> arc_to_pip;
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ArcVector arcs;
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ExtendedWireInfo ewi(*ddb);
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PipId p;
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p.index = 0;
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for (w.index = 0; w.index < num_wires; ++w.index) {
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const auto ¤tTilewire = wire_to_tilewire[w.index];
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if (currentTilewire.isUndefined())
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continue;
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const auto &tileInfo = tiles.getTileInfo(currentTilewire.getTileIndex());
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const auto tileTypeName = tiles.getTileTypeName(tileInfo.getTypeIndex());
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const bool clb = boost::starts_with(
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tileTypeName, "CLB"); // Disable all CLB route-throughs (i.e. LUT in->out, LUT A->AMUX, for now)
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arcs.clear();
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const_cast<DDB &>(*ddb).expandSegmentSinks(currentTilewire, arcs, DDB::eExpandDirectionNone,
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false /* inUseTied */, true /*inUseRegular */,
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true /* inUseIrregular */, !clb /* inUseRoutethrough */);
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auto &pips = wire_to_pips_downhill[w.index];
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pips.reserve(arcs.size());
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const bool clk_tile = boost::starts_with(tileTypeName, "CMT") || boost::starts_with(tileTypeName, "CLK");
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const bool int_tile = boost::starts_with(tileTypeName, "INT");
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for (const auto &a : arcs) {
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// Disable BUFG I0 -> O routethrough
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if (clk_tile) {
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ewi.set(a.getSourceTilewire());
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if (boost::regex_match(ewi.mWireName, bufg_i)) {
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ewi.set(a.getSinkTilewire());
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if (boost::regex_match(ewi.mWireName, bufg_o))
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continue;
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}
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}
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// Disable CLK inputs from being driven from the fabric (must be from global clock network)
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else if (int_tile) {
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ewi.set(a.getSinkTilewire());
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if (boost::regex_match(ewi.mWireName, int_clk)) {
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ewi.set(a.getSourceTilewire());
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if (!boost::regex_match(ewi.mWireName, gclk))
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continue;
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}
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}
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pips.emplace_back(p);
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pip_to_arc.emplace_back(a);
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// arc_to_pip.emplace(a, p.index);
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const auto &tw = a.getSinkTilewire();
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pip_to_dst_wire.emplace_back(tilewire_to_wire(tw));
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++p.index;
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}
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pips.shrink_to_fit();
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}
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pip_to_arc.shrink_to_fit();
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num_pips = pip_to_arc.size();
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pip_to_dst_wire.reserve(num_pips);
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for (const auto &arc : pip_to_arc) {
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const auto &tw = arc.getSinkTilewire();
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pip_to_dst_wire.emplace_back(tilewire_to_wire(tw));
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}
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height = (int)tiles.getRowCount();
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width = (int)tiles.getColCount();
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}
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TorcInfo::TorcInfo(const std::string& inDeviceName, const std::string &inPackageName)
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: ddb(new DDB(inDeviceName, inPackageName)), sites(ddb->getSites()), tiles(ddb->getTiles()),
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segments(ddb->getSegments())
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{
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}
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// -----------------------------------------------------------------------
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void IdString::initialize_arch(const BaseCtx *ctx)
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{
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#define X(t) initialize_add(ctx, #t, ID_##t);
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#include "constids.inc"
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#undef X
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}
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// -----------------------------------------------------------------------
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Arch::Arch(ArchArgs args) : args(args)
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{
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torc::common::DirectoryTree directoryTree("/opt/torc/src/torc");
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if (args.type == ArchArgs::Z020) {
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#ifdef TORC_INFO_DB
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std::ifstream ifs(TORC_INFO_DB, std::ios::binary);
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if (ifs) {
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boost::iostreams::filtering_istreambuf fifs;
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fifs.push(boost::iostreams::zlib_decompressor());
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fifs.push(ifs);
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nextpnr_binary_iarchive ia(fifs, this, "xc7z020", args.package);
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ia >> torc_info;
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} else
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#endif
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{
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torc_info = std::unique_ptr<TorcInfo>(new TorcInfo(this, "xc7z020", args.package));
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#ifdef TORC_INFO_DB
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std::ofstream ofs(TORC_INFO_DB, std::ios::binary);
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if (ofs) {
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boost::iostreams::filtering_ostreambuf fofs;
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fofs.push(boost::iostreams::zlib_compressor());
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fofs.push(ofs);
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nextpnr_binary_oarchive oa(fofs, this);
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oa << torc_info;
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}
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#endif
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}
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} else {
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log_error("Unsupported XC7 chip type.\n");
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}
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width = torc_info->width;
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height = torc_info->height;
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/*if (getCtx()->verbose)*/ {
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log_info("Number of bels: %d\n", torc_info->num_bels);
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log_info("Number of wires: %d\n", torc_info->num_wires);
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log_info("Number of pips: %d\n", torc_info->num_pips);
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}
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// package_info = nullptr;
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// for (int i = 0; i < chip_info->num_packages; i++) {
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// if (chip_info->packages_data[i].name.get() == args.package) {
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// package_info = &(chip_info->packages_data[i]);
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// break;
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// }
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// }
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// if (package_info == nullptr)
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// log_error("Unsupported package '%s'.\n", args.package.c_str());
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// bel_carry.resize(chip_info->num_bels);
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bel_to_cell.resize(torc_info->num_bels);
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wire_to_net.resize(torc_info->num_wires);
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pip_to_net.resize(torc_info->num_pips);
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// switches_locked.resize(chip_info->num_switches);
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}
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// -----------------------------------------------------------------------
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std::string Arch::getChipName() const
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{
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if (args.type == ArchArgs::Z020) {
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return "z020";
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} else {
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log_error("Unsupported XC7 chip type.\n");
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}
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}
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// -----------------------------------------------------------------------
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IdString Arch::archArgsToId(ArchArgs args) const
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{
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if (args.type == ArchArgs::Z020)
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return id("z020");
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return IdString();
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}
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// -----------------------------------------------------------------------
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BelId Arch::getBelByName(IdString name) const
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{
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auto it = torc_info->sites.findSiteIndex(name.str(this));
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if (it != SiteIndex(-1))
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return torc_info->site_index_to_bel.at(it);
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return BelId();
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}
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BelId Arch::getBelByLocation(Loc loc) const
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{
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BelId bel;
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if (bel_by_loc.empty()) {
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for (int i = 0; i < torc_info->num_bels; i++) {
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BelId b;
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b.index = i;
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bel_by_loc[getBelLocation(b)] = b;
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}
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}
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auto it = bel_by_loc.find(loc);
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if (it != bel_by_loc.end())
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bel = it->second;
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return bel;
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}
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BelRange Arch::getBelsByTile(int x, int y) const
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{
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BelRange br;
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br.b.cursor = Arch::getBelByLocation(Loc(x, y, 0)).index;
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br.e.cursor = br.b.cursor;
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if (br.e.cursor != -1) {
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while (br.e.cursor < chip_info->num_bels && chip_info->bel_data[br.e.cursor].x == x &&
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chip_info->bel_data[br.e.cursor].y == y)
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br.e.cursor++;
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}
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return br;
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}
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PortType Arch::getBelPinType(BelId bel, IdString pin) const
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{
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NPNR_ASSERT(bel != BelId());
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int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
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const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
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if (num_bel_wires < 7) {
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for (int i = 0; i < num_bel_wires; i++) {
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if (bel_wires[i].port == pin.index)
|
|
return PortType(bel_wires[i].type);
|
|
}
|
|
} else {
|
|
int b = 0, e = num_bel_wires - 1;
|
|
while (b <= e) {
|
|
int i = (b + e) / 2;
|
|
if (bel_wires[i].port == pin.index)
|
|
return PortType(bel_wires[i].type);
|
|
if (bel_wires[i].port > pin.index)
|
|
e = i - 1;
|
|
else
|
|
b = i + 1;
|
|
}
|
|
}
|
|
|
|
return PORT_INOUT;
|
|
}
|
|
|
|
std::vector<std::pair<IdString, std::string>> Arch::getBelAttrs(BelId bel) const
|
|
{
|
|
std::vector<std::pair<IdString, std::string>> ret;
|
|
return ret;
|
|
}
|
|
|
|
WireId Arch::getBelPinWire(BelId bel, IdString pin) const
|
|
{
|
|
auto pin_name = pin.str(this);
|
|
auto bel_type = getBelType(bel);
|
|
if (bel_type == id_SLICE_LUT6) {
|
|
// For all LUT based inputs and outputs (I1-I6,O,OQ,OMUX) then change the I/O into the LUT
|
|
if (pin_name[0] == 'I' || pin_name[0] == 'O') {
|
|
switch (torc_info->bel_to_loc[bel.index].z) {
|
|
case 0:
|
|
case 4:
|
|
pin_name[0] = 'A';
|
|
break;
|
|
case 1:
|
|
case 5:
|
|
pin_name[0] = 'B';
|
|
break;
|
|
case 2:
|
|
case 6:
|
|
pin_name[0] = 'C';
|
|
break;
|
|
case 3:
|
|
case 7:
|
|
pin_name[0] = 'D';
|
|
break;
|
|
default:
|
|
throw;
|
|
}
|
|
}
|
|
} else if (bel_type == id_PS7 || bel_type == id_MMCME2_ADV) {
|
|
// e.g. Convert DDRARB[0] -> DDRARB0
|
|
pin_name.erase(std::remove_if(pin_name.begin(), pin_name.end(), boost::is_any_of("[]")), pin_name.end());
|
|
}
|
|
|
|
auto site_index = torc_info->bel_to_site_index[bel.index];
|
|
const auto &site = torc_info->sites.getSite(site_index);
|
|
auto &tw = site.getPinTilewire(pin_name);
|
|
|
|
if (tw.isUndefined())
|
|
log_error("no wire found for site '%s' pin '%s' \n", torc_info->bel_to_name(bel.index).c_str(),
|
|
pin_name.c_str());
|
|
|
|
return torc_info->tilewire_to_wire(tw);
|
|
|
|
// NPNR_ASSERT(bel != BelId());
|
|
//
|
|
// int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
|
|
// const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
|
|
//
|
|
// if (num_bel_wires < 7) {
|
|
// for (int i = 0; i < num_bel_wires; i++) {
|
|
// if (bel_wires[i].port == pin.index) {
|
|
// ret.index = bel_wires[i].wire_index;
|
|
// break;
|
|
// }
|
|
// }
|
|
// } else {
|
|
// int b = 0, e = num_bel_wires - 1;
|
|
// while (b <= e) {
|
|
// int i = (b + e) / 2;
|
|
// if (bel_wires[i].port == pin.index) {
|
|
// ret.index = bel_wires[i].wire_index;
|
|
// break;
|
|
// }
|
|
// if (bel_wires[i].port > pin.index)
|
|
// e = i - 1;
|
|
// else
|
|
// b = i + 1;
|
|
// }
|
|
// }
|
|
//
|
|
//return ret;
|
|
}
|
|
|
|
std::vector<IdString> Arch::getBelPins(BelId bel) const
|
|
{
|
|
std::vector<IdString> ret;
|
|
|
|
/* NPNR_ASSERT(bel != BelId());
|
|
|
|
int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
|
|
const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
|
|
|
|
for (int i = 0; i < num_bel_wires; i++)
|
|
ret.push_back(IdString(bel_wires[i].port));
|
|
*/
|
|
return ret;
|
|
}
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
WireId Arch::getWireByName(IdString name) const
|
|
{
|
|
WireId ret;
|
|
|
|
if (wire_by_name.empty()) {
|
|
for (int i = 0; i < chip_info->num_wires; i++)
|
|
wire_by_name[id(chip_info->wire_data[i].name.get())] = i;
|
|
}
|
|
|
|
// auto it = wire_by_name.find(name);
|
|
// if (it != wire_by_name.end())
|
|
// ret.index = it->second;
|
|
|
|
return ret;
|
|
}
|
|
|
|
IdString Arch::getWireType(WireId wire) const
|
|
{
|
|
NPNR_ASSERT(wire != WireId());
|
|
// switch (chip_info->wire_data[wire.index].type) {
|
|
// case WireInfoPOD::WIRE_TYPE_NONE:
|
|
// return IdString();
|
|
// case WireInfoPOD::WIRE_TYPE_GLB2LOCAL:
|
|
// return id("GLB2LOCAL");
|
|
// case WireInfoPOD::WIRE_TYPE_GLB_NETWK:
|
|
// return id("GLB_NETWK");
|
|
// case WireInfoPOD::WIRE_TYPE_LOCAL:
|
|
// return id("LOCAL");
|
|
// case WireInfoPOD::WIRE_TYPE_LUTFF_IN:
|
|
// return id("LUTFF_IN");
|
|
// case WireInfoPOD::WIRE_TYPE_LUTFF_IN_LUT:
|
|
// return id("LUTFF_IN_LUT");
|
|
// case WireInfoPOD::WIRE_TYPE_LUTFF_LOUT:
|
|
// return id("LUTFF_LOUT");
|
|
// case WireInfoPOD::WIRE_TYPE_LUTFF_OUT:
|
|
// return id("LUTFF_OUT");
|
|
// case WireInfoPOD::WIRE_TYPE_LUTFF_COUT:
|
|
// return id("LUTFF_COUT");
|
|
// case WireInfoPOD::WIRE_TYPE_LUTFF_GLOBAL:
|
|
// return id("LUTFF_GLOBAL");
|
|
// case WireInfoPOD::WIRE_TYPE_CARRY_IN_MUX:
|
|
// return id("CARRY_IN_MUX");
|
|
// case WireInfoPOD::WIRE_TYPE_SP4_V:
|
|
// return id("SP4_V");
|
|
// case WireInfoPOD::WIRE_TYPE_SP4_H:
|
|
// return id("SP4_H");
|
|
// case WireInfoPOD::WIRE_TYPE_SP12_V:
|
|
// return id("SP12_V");
|
|
// case WireInfoPOD::WIRE_TYPE_SP12_H:
|
|
// return id("SP12_H");
|
|
// }
|
|
return IdString();
|
|
}
|
|
|
|
// -----------------------------------------------------------------------
|
|
std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const
|
|
{
|
|
std::vector<std::pair<IdString, std::string>> ret;
|
|
return ret;
|
|
}
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
PipId Arch::getPipByName(IdString name) const
|
|
{
|
|
PipId ret;
|
|
|
|
/* if (pip_by_name.empty()) {
|
|
for (int i = 0; i < chip_info->num_pips; i++) {
|
|
PipId pip;
|
|
pip.index = i;
|
|
pip_by_name[getPipName(pip)] = i;
|
|
}
|
|
}
|
|
|
|
auto it = pip_by_name.find(name);
|
|
if (it != pip_by_name.end())
|
|
ret.index = it->second;
|
|
*/
|
|
return ret;
|
|
}
|
|
|
|
IdString Arch::getPipName(PipId pip) const
|
|
{
|
|
NPNR_ASSERT(pip != PipId());
|
|
|
|
ExtendedWireInfo ewi_src(*torc_info->ddb, torc_info->pip_to_arc[pip.index].getSourceTilewire());
|
|
ExtendedWireInfo ewi_dst(*torc_info->ddb, torc_info->pip_to_arc[pip.index].getSinkTilewire());
|
|
std::stringstream pip_name;
|
|
pip_name << ewi_src.mTileName << "." << ewi_src.mWireName << ".->." << ewi_dst.mWireName;
|
|
return id(pip_name.str());
|
|
|
|
//#if 1
|
|
// int x = chip_info->pip_data[pip.index].x;
|
|
// int y = chip_info->pip_data[pip.index].y;
|
|
//
|
|
// std::string src_name = chip_info->wire_data[chip_info->pip_data[pip.index].src].name.get();
|
|
// std::replace(src_name.begin(), src_name.end(), '/', '.');
|
|
//
|
|
// std::string dst_name = chip_info->wire_data[chip_info->pip_data[pip.index].dst].name.get();
|
|
// std::replace(dst_name.begin(), dst_name.end(), '/', '.');
|
|
//
|
|
// return id("X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" + src_name + ".->." + dst_name);
|
|
//#else
|
|
// return id(chip_info->pip_data[pip.index].name.get());
|
|
//#endif
|
|
}
|
|
|
|
std::vector<std::pair<IdString, std::string>> Arch::getPipAttrs(PipId pip) const
|
|
{
|
|
std::vector<std::pair<IdString, std::string>> ret;
|
|
|
|
return ret;
|
|
}
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
BelId Arch::getPackagePinBel(const std::string &pin) const { return getBelByName(id(pin)); }
|
|
|
|
std::string Arch::getBelPackagePin(BelId bel) const
|
|
{
|
|
// for (int i = 0; i < package_info->num_pins; i++) {
|
|
// if (package_info->pins[i].bel_index == bel.index) {
|
|
// return std::string(package_info->pins[i].name.get());
|
|
// }
|
|
// }
|
|
return "";
|
|
}
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
GroupId Arch::getGroupByName(IdString name) const
|
|
{
|
|
for (auto g : getGroups())
|
|
if (getGroupName(g) == name)
|
|
return g;
|
|
return GroupId();
|
|
}
|
|
|
|
IdString Arch::getGroupName(GroupId group) const
|
|
{
|
|
std::string suffix;
|
|
|
|
switch (group.type) {
|
|
case GroupId::TYPE_FRAME:
|
|
suffix = "tile";
|
|
break;
|
|
case GroupId::TYPE_MAIN_SW:
|
|
suffix = "main_sw";
|
|
break;
|
|
case GroupId::TYPE_LOCAL_SW:
|
|
suffix = "local_sw";
|
|
break;
|
|
case GroupId::TYPE_LC0_SW:
|
|
suffix = "lc0_sw";
|
|
break;
|
|
case GroupId::TYPE_LC1_SW:
|
|
suffix = "lc1_sw";
|
|
break;
|
|
case GroupId::TYPE_LC2_SW:
|
|
suffix = "lc2_sw";
|
|
break;
|
|
case GroupId::TYPE_LC3_SW:
|
|
suffix = "lc3_sw";
|
|
break;
|
|
case GroupId::TYPE_LC4_SW:
|
|
suffix = "lc4_sw";
|
|
break;
|
|
case GroupId::TYPE_LC5_SW:
|
|
suffix = "lc5_sw";
|
|
break;
|
|
case GroupId::TYPE_LC6_SW:
|
|
suffix = "lc6_sw";
|
|
break;
|
|
case GroupId::TYPE_LC7_SW:
|
|
suffix = "lc7_sw";
|
|
break;
|
|
default:
|
|
return IdString();
|
|
}
|
|
|
|
return id("X" + std::to_string(group.x) + "/Y" + std::to_string(group.y) + "/" + suffix);
|
|
}
|
|
|
|
std::vector<GroupId> Arch::getGroups() const
|
|
{
|
|
std::vector<GroupId> ret;
|
|
/*
|
|
for (int y = 0; y < chip_info->height; y++) {
|
|
for (int x = 0; x < chip_info->width; x++) {
|
|
TileType type = chip_info->tile_grid[y * chip_info->width + x];
|
|
if (type == TILE_NONE)
|
|
continue;
|
|
|
|
GroupId group;
|
|
group.type = GroupId::TYPE_FRAME;
|
|
group.x = x;
|
|
group.y = y;
|
|
// ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_MAIN_SW;
|
|
ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_LOCAL_SW;
|
|
ret.push_back(group);
|
|
|
|
if (type == TILE_LOGIC) {
|
|
group.type = GroupId::TYPE_LC0_SW;
|
|
ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_LC1_SW;
|
|
ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_LC2_SW;
|
|
ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_LC3_SW;
|
|
ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_LC4_SW;
|
|
ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_LC5_SW;
|
|
ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_LC6_SW;
|
|
ret.push_back(group);
|
|
|
|
group.type = GroupId::TYPE_LC7_SW;
|
|
ret.push_back(group);
|
|
}
|
|
}
|
|
}*/
|
|
return ret;
|
|
}
|
|
|
|
std::vector<BelId> Arch::getGroupBels(GroupId group) const
|
|
{
|
|
std::vector<BelId> ret;
|
|
return ret;
|
|
}
|
|
|
|
std::vector<WireId> Arch::getGroupWires(GroupId group) const
|
|
{
|
|
std::vector<WireId> ret;
|
|
return ret;
|
|
}
|
|
|
|
std::vector<PipId> Arch::getGroupPips(GroupId group) const
|
|
{
|
|
std::vector<PipId> ret;
|
|
return ret;
|
|
}
|
|
|
|
std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
|
|
{
|
|
std::vector<GroupId> ret;
|
|
return ret;
|
|
}
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); }
|
|
|
|
bool Arch::route() { return router1(getCtx(), Router1Cfg(getCtx())); }
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
DecalXY Arch::getBelDecal(BelId bel) const
|
|
{
|
|
DecalXY decalxy;
|
|
decalxy.decal.type = DecalId::TYPE_BEL;
|
|
decalxy.decal.index = bel.index;
|
|
decalxy.decal.active = bel_to_cell.at(bel.index) != nullptr;
|
|
return decalxy;
|
|
}
|
|
|
|
DecalXY Arch::getWireDecal(WireId wire) const
|
|
{
|
|
DecalXY decalxy;
|
|
decalxy.decal.type = DecalId::TYPE_WIRE;
|
|
decalxy.decal.index = wire.index;
|
|
decalxy.decal.active = wire_to_net.at(wire.index) != nullptr;
|
|
return decalxy;
|
|
}
|
|
|
|
DecalXY Arch::getPipDecal(PipId pip) const
|
|
{
|
|
DecalXY decalxy;
|
|
decalxy.decal.type = DecalId::TYPE_PIP;
|
|
decalxy.decal.index = pip.index;
|
|
decalxy.decal.active = pip_to_net.at(pip.index) != nullptr;
|
|
return decalxy;
|
|
};
|
|
|
|
DecalXY Arch::getGroupDecal(GroupId group) const
|
|
{
|
|
DecalXY decalxy;
|
|
decalxy.decal.type = DecalId::TYPE_GROUP;
|
|
decalxy.decal.index = (group.type << 16) | (group.x << 8) | (group.y);
|
|
decalxy.decal.active = true;
|
|
return decalxy;
|
|
};
|
|
|
|
std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
|
|
{
|
|
std::vector<GraphicElement> ret;
|
|
return ret;
|
|
}
|
|
|
|
// -----------------------------------------------------------------------
|
|
|
|
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
|
|
{
|
|
if (cell->type == id_SLICE_LUT6) {
|
|
if (fromPort.index >= id_I1.index && fromPort.index <= id_I6.index) {
|
|
if (toPort == id_O) {
|
|
delay.delay = 124; // Tilo
|
|
return true;
|
|
}
|
|
if (toPort == id_OQ) {
|
|
delay.delay = 95; // Tas
|
|
return true;
|
|
}
|
|
}
|
|
if (fromPort == id_CLK) {
|
|
if (toPort == id_OQ) {
|
|
delay.delay = 456; // Tcko
|
|
return true;
|
|
}
|
|
}
|
|
} else if (cell->type == id_BUFGCTRL) {
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
// Get the port class, also setting clockPort to associated clock if applicable
|
|
TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
|
|
{
|
|
if (cell->type == id_SLICE_LUT6) {
|
|
if (port == id_CLK)
|
|
return TMG_CLOCK_INPUT;
|
|
if (port == id_CIN)
|
|
return TMG_COMB_INPUT;
|
|
if (port == id_COUT)
|
|
return TMG_COMB_OUTPUT;
|
|
if (port == id_O) {
|
|
// LCs with no inputs are constant drivers
|
|
if (cell->lcInfo.inputCount == 0)
|
|
return TMG_IGNORE;
|
|
return TMG_COMB_OUTPUT;
|
|
}
|
|
if (cell->lcInfo.dffEnable) {
|
|
clockInfoCount = 1;
|
|
if (port == id_OQ)
|
|
return TMG_REGISTER_OUTPUT;
|
|
return TMG_REGISTER_INPUT;
|
|
} else {
|
|
return TMG_COMB_INPUT;
|
|
}
|
|
// TODO
|
|
// if (port == id_OMUX)
|
|
} else if (cell->type == id_IOB33) {
|
|
if (port == id_I)
|
|
return TMG_STARTPOINT;
|
|
else if (port == id_O)
|
|
return TMG_ENDPOINT;
|
|
} else if (cell->type == id_BUFGCTRL) {
|
|
if (port == id_O)
|
|
return TMG_COMB_OUTPUT;
|
|
return TMG_COMB_INPUT;
|
|
} else if (cell->type == id_PS7) {
|
|
// TODO
|
|
return TMG_IGNORE;
|
|
} else if (cell->type == id_MMCME2_ADV) {
|
|
return TMG_IGNORE;
|
|
}
|
|
log_error("no timing info for port '%s' of cell type '%s'\n", port.c_str(this), cell->type.c_str(this));
|
|
}
|
|
|
|
TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
|
|
{
|
|
TimingClockingInfo info;
|
|
if (cell->type == id_SLICE_LUT6) {
|
|
info.clock_port = id_CLK;
|
|
info.edge = cell->lcInfo.negClk ? FALLING_EDGE : RISING_EDGE;
|
|
if (port == id_OQ) {
|
|
bool has_clktoq = getCellDelay(cell, id_CLK, id_OQ, info.clockToQ);
|
|
NPNR_ASSERT(has_clktoq);
|
|
} else {
|
|
info.setup.delay = 124; // Tilo
|
|
info.hold.delay = 0;
|
|
}
|
|
} else {
|
|
NPNR_ASSERT_FALSE("unhandled cell type in getPortClockingInfo");
|
|
}
|
|
return info;
|
|
}
|
|
|
|
bool Arch::isGlobalNet(const NetInfo *net) const
|
|
{
|
|
if (net == nullptr)
|
|
return false;
|
|
return net->driver.cell != nullptr && net->driver.cell->type == id_BUFGCTRL && net->driver.port == id_O;
|
|
}
|
|
|
|
// Assign arch arg info
|
|
void Arch::assignArchInfo()
|
|
{
|
|
for (auto &net : getCtx()->nets) {
|
|
NetInfo *ni = net.second.get();
|
|
if (isGlobalNet(ni))
|
|
ni->is_global = true;
|
|
ni->is_enable = false;
|
|
ni->is_reset = false;
|
|
for (auto usr : ni->users) {
|
|
if (is_enable_port(this, usr))
|
|
ni->is_enable = true;
|
|
if (is_reset_port(this, usr))
|
|
ni->is_reset = true;
|
|
}
|
|
}
|
|
for (auto &cell : getCtx()->cells) {
|
|
CellInfo *ci = cell.second.get();
|
|
assignCellInfo(ci);
|
|
}
|
|
}
|
|
|
|
void Arch::assignCellInfo(CellInfo *cell)
|
|
{
|
|
cell->belType = cell->type;
|
|
if (cell->type == id_SLICE_LUT6) {
|
|
cell->lcInfo.dffEnable = bool_or_default(cell->params, id_DFF_ENABLE);
|
|
cell->lcInfo.carryEnable = bool_or_default(cell->params, id_CARRY_ENABLE);
|
|
cell->lcInfo.negClk = bool_or_default(cell->params, id_NEG_CLK);
|
|
cell->lcInfo.clk = get_net_or_empty(cell, id_CLK);
|
|
cell->lcInfo.cen = get_net_or_empty(cell, id_CEN);
|
|
cell->lcInfo.sr = get_net_or_empty(cell, id_SR);
|
|
cell->lcInfo.inputCount = 0;
|
|
if (get_net_or_empty(cell, id_I1))
|
|
cell->lcInfo.inputCount++;
|
|
if (get_net_or_empty(cell, id_I2))
|
|
cell->lcInfo.inputCount++;
|
|
if (get_net_or_empty(cell, id_I3))
|
|
cell->lcInfo.inputCount++;
|
|
if (get_net_or_empty(cell, id_I4))
|
|
cell->lcInfo.inputCount++;
|
|
if (get_net_or_empty(cell, id_I5))
|
|
cell->lcInfo.inputCount++;
|
|
if (get_net_or_empty(cell, id_I6))
|
|
cell->lcInfo.inputCount++;
|
|
}
|
|
}
|
|
|
|
NEXTPNR_NAMESPACE_END
|
|
|
|
// outside of any namespace
|
|
BOOST_SERIALIZATION_SPLIT_FREE(Segments::SegmentReference)
|
|
BOOST_SERIALIZATION_SPLIT_FREE(CompactSegmentIndex)
|
|
BOOST_SERIALIZATION_SPLIT_FREE(TileIndex)
|
|
BOOST_SERIALIZATION_SPLIT_FREE(Arc)
|
|
BOOST_SERIALIZATION_SPLIT_FREE(Tilewire)
|
|
BOOST_SERIALIZATION_SPLIT_FREE(WireIndex)
|
|
BOOST_SERIALIZATION_SPLIT_FREE(SiteIndex)
|
|
BOOST_SERIALIZATION_SPLIT_FREE(NEXTPNR_NAMESPACE::IdString)
|
|
|
|
namespace boost { namespace serialization {
|
|
|
|
template<class Archive>
|
|
inline void load_construct_data(
|
|
Archive & ar, NEXTPNR_NAMESPACE::TorcInfo * t, const unsigned int file_version
|
|
){
|
|
const auto& inDeviceName = static_cast<const nextpnr_binary_iarchive&>(ar).inDeviceName;
|
|
const auto& inPackageName = static_cast<const nextpnr_binary_iarchive&>(ar).inPackageName;
|
|
::new(t)NEXTPNR_NAMESPACE::TorcInfo(inDeviceName, inPackageName);
|
|
}
|
|
|
|
template<class Archive>
|
|
void save(Archive& ar, const Segments::SegmentReference& o, unsigned int) {
|
|
ar & o.getCompactSegmentIndex();
|
|
ar & o.getAnchorTileIndex();
|
|
}
|
|
template<class Archive>
|
|
void load(Archive& ar, Segments::SegmentReference& o, unsigned int) {
|
|
CompactSegmentIndex i;
|
|
TileIndex j;
|
|
ar & i;
|
|
ar & j;
|
|
o = Segments::SegmentReference(i, j);
|
|
}
|
|
#define SERIALIZE_POD(__T__) \
|
|
template<class Archive> \
|
|
void save(Archive& ar, const __T__& o, unsigned int) { \
|
|
ar & static_cast<__T__::pod>(o); \
|
|
} \
|
|
template<class Archive> \
|
|
void load(Archive& ar, __T__& o, unsigned int) { \
|
|
__T__::pod i; \
|
|
ar & i; \
|
|
o = __T__(i); \
|
|
}
|
|
SERIALIZE_POD(CompactSegmentIndex)
|
|
SERIALIZE_POD(TileIndex)
|
|
SERIALIZE_POD(WireIndex)
|
|
SERIALIZE_POD(SiteIndex)
|
|
template<class Archive>
|
|
void save(Archive& ar, const Arc& o, unsigned int) {
|
|
ar & o.getSourceTilewire();
|
|
ar & o.getSinkTilewire();
|
|
}
|
|
template<class Archive>
|
|
void load(Archive& ar, Arc& o, unsigned int) {
|
|
Tilewire s, t;
|
|
ar & s;
|
|
ar & t;
|
|
o = Arc(s, t);
|
|
}
|
|
template<class Archive>
|
|
void save(Archive& ar, const Tilewire& o, unsigned int) {
|
|
ar & o.getTileIndex();
|
|
ar & o.getWireIndex();
|
|
}
|
|
template<class Archive>
|
|
void load(Archive& ar, Tilewire& o, unsigned int) {
|
|
TileIndex i;
|
|
WireIndex j;
|
|
ar & i;
|
|
ar & j;
|
|
o.setTileIndex(TileIndex(i));
|
|
o.setWireIndex(WireIndex(j));
|
|
}
|
|
template<class Archive>
|
|
void serialize(Archive& ar, NEXTPNR_NAMESPACE::Loc& o, unsigned int) {
|
|
ar & o.x;
|
|
ar & o.y;
|
|
ar & o.z;
|
|
}
|
|
template<class Archive>
|
|
void serialize(Archive& ar, NEXTPNR_NAMESPACE::DelayInfo& o, unsigned int) {
|
|
ar & o.delay;
|
|
}
|
|
template<class Archive>
|
|
void save(Archive& ar, const NEXTPNR_NAMESPACE::IdString& o, unsigned int) {
|
|
const std::string i = o.str(static_cast<const nextpnr_binary_oarchive&>(ar).ctx);
|
|
ar & i;
|
|
}
|
|
template<class Archive>
|
|
void load(Archive& ar, NEXTPNR_NAMESPACE::IdString& o, unsigned int) {
|
|
std::string i;
|
|
ar & i;
|
|
o = static_cast<nextpnr_binary_iarchive&>(ar).ctx->id(i);
|
|
}
|
|
#define SERIALIZE_INDEX(__T__) \
|
|
template<class Archive> \
|
|
void serialize(Archive& ar, __T__& o, unsigned int) { \
|
|
ar & o.index; \
|
|
}
|
|
SERIALIZE_INDEX(NEXTPNR_NAMESPACE::BelId)
|
|
SERIALIZE_INDEX(NEXTPNR_NAMESPACE::WireId)
|
|
SERIALIZE_INDEX(NEXTPNR_NAMESPACE::PipId)
|
|
}} // namespace boost::serialization
|