251 lines
8.7 KiB
C++
251 lines
8.7 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021 Lofty <dan.ravensloft@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef MISTRAL_ARCH_H
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#define MISTRAL_ARCH_H
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#include <set>
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#include <sstream>
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#include "base_arch.h"
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#include "nextpnr_types.h"
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#include "relptr.h"
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#include "cyclonev.h"
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NEXTPNR_NAMESPACE_BEGIN
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struct ArchArgs
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{
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std::string device;
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std::string mistral_root;
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};
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struct PinInfo
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{
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IdString name;
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WireId wire;
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PortType type;
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};
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struct BelInfo
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{
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// TODO
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};
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struct WireInfo
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{
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// name_override is only used for nextpnr-created wires
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// otherwise; this is empty and a name is created according to mistral rules
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IdString name_override;
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// these are transformed on-the-fly to PipId by the iterator, to save space (WireId is half the size of PipId)
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std::vector<WireId> wires_downhill;
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std::vector<WireId> wires_uphill;
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std::vector<BelPin> bel_pins;
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// flags for special wires (currently unused)
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uint64_t flags;
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};
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// This transforms a WireIds, and adds the mising half of the pair to create a PipId
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using WireVecIterator = std::vector<WireId>::const_iterator;
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struct UpDownhillPipIterator
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{
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WireVecIterator base;
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WireId other_wire;
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bool is_uphill;
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UpDownhillPipIterator(WireVecIterator base, WireId other_wire, bool is_uphill)
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: base(base), other_wire(other_wire), is_uphill(is_uphill){};
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bool operator!=(const UpDownhillPipIterator &other) { return base != other.base; }
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UpDownhillPipIterator operator++()
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{
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++base;
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return *this;
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}
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UpDownhillPipIterator operator++(int)
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{
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UpDownhillPipIterator prior(*this);
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++(*this);
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return prior;
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}
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PipId operator*() { return is_uphill ? PipId(base->node, other_wire.node) : PipId(other_wire.node, base->node); }
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};
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struct UpDownhillPipRange
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{
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UpDownhillPipIterator b, e;
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UpDownhillPipRange(const std::vector<WireId> &v, WireId other_wire, bool is_uphill)
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: b(v.cbegin(), other_wire, is_uphill), e(v.cend(), other_wire, is_uphill){};
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UpDownhillPipIterator begin() const { return b; }
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UpDownhillPipIterator end() const { return e; }
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};
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// This transforms a map to a range of keys, used as the wire iterator
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template <typename T> struct key_range
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{
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key_range(const T &t) : b(t.cbegin()), e(t.cend()){};
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typename T::const_iterator b, e;
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struct xformed_iterator : public T::const_iterator
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{
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explicit xformed_iterator(typename T::const_iterator base) : T::const_iterator(base){};
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typename T::key_type operator*() { return this->T::const_iterator::operator*().first; }
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};
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xformed_iterator begin() const { return xformed_iterator(b); }
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xformed_iterator end() const { return xformed_iterator(e); }
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};
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using AllWireRange = key_range<std::unordered_map<WireId, WireInfo>>;
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using AllBelRange = key_range<std::unordered_map<BelId, BelInfo>>;
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struct ArchRanges : BaseArchRanges
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{
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using ArchArgsT = ArchArgs;
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// Bels
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using AllBelsRangeT = AllBelRange;
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using TileBelsRangeT = std::vector<BelId>;
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using BelPinsRangeT = std::vector<IdString>;
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// Wires
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using AllWiresRangeT = AllWireRange;
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using DownhillPipRangeT = UpDownhillPipRange;
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using UphillPipRangeT = UpDownhillPipRange;
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using WireBelPinRangeT = const std::vector<BelPin> &;
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// Pips
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using AllPipsRangeT = const std::unordered_set<PipId> &;
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};
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struct Arch : BaseArch<ArchRanges>
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{
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ArchArgs args;
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mistral::CycloneV *cyclonev;
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Arch(ArchArgs args);
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ArchArgs archArgs() const { return args; }
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std::string getChipName() const override { return std::string{"TODO: getChipName"}; }
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// -------------------------------------------------
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int getGridDimX() const override { return cyclonev->get_tile_sx(); }
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int getGridDimY() const override { return cyclonev->get_tile_sy(); }
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int getTileBelDimZ(int x, int y) const override; // arch.cc
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char getNameDelimiter() const override { return '.'; }
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// -------------------------------------------------
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BelId getBelByName(IdStringList name) const override; // arch.cc
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IdStringList getBelName(BelId bel) const override; // arch.cc
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AllBelRange getBels() const override { return AllBelRange(bels); }
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std::vector<BelId> getBelsByTile(int x, int y) const override;
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Loc getBelLocation(BelId bel) const override
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{
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return Loc(CycloneV::pos2x(bel.pos), CycloneV::pos2y(bel.pos), bel.z);
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}
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BelId getBelByLocation(Loc loc) const override
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{
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BelId id = BelId(CycloneV::xy2pos(loc.x, loc.y), loc.z);
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if (bels.count(id))
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return id;
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else
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return BelId();
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}
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IdString getBelType(BelId bel) const override; // arch.cc
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WireId getBelPinWire(BelId bel, IdString pin) const override { return WireId(); }
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PortType getBelPinType(BelId bel, IdString pin) const override { return PORT_IN; }
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std::vector<IdString> getBelPins(BelId bel) const override { return {}; }
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// -------------------------------------------------
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WireId getWireByName(IdStringList name) const override;
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IdStringList getWireName(WireId wire) const override;
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DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0); }
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const std::vector<BelPin> &getWireBelPins(WireId wire) const override { return empty_belpin_list; }
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AllWireRange getWires() const override { return AllWireRange(wires); }
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// -------------------------------------------------
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PipId getPipByName(IdStringList name) const override;
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const std::unordered_set<PipId> &getPips() const override { return all_pips; }
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Loc getPipLocation(PipId pip) const override { return Loc(0, 0, 0); }
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IdStringList getPipName(PipId pip) const override;
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WireId getPipSrcWire(PipId pip) const override { return WireId(pip.src); };
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WireId getPipDstWire(PipId pip) const override { return WireId(pip.dst); };
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DelayQuad getPipDelay(PipId pip) const override { return DelayQuad(0); }
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UpDownhillPipRange getPipsDownhill(WireId wire) const override
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{
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return UpDownhillPipRange(wires.at(wire).wires_downhill, wire, false);
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}
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UpDownhillPipRange getPipsUphill(WireId wire) const override
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{
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return UpDownhillPipRange(wires.at(wire).wires_uphill, wire, true);
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}
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// -------------------------------------------------
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delay_t estimateDelay(WireId src, WireId dst) const override { return 100; };
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delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override { return 100; };
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delay_t getDelayEpsilon() const override { return 10; };
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delay_t getRipupDelayPenalty() const override { return 100; };
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float getDelayNS(delay_t v) const override { return float(v) / 1000.0f; };
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delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000.0f); };
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uint32_t getDelayChecksum(delay_t v) const override { return v; };
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ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override { return ArcBounds(); }
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// -------------------------------------------------
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bool pack() override;
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bool place() override;
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bool route() override;
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// -------------------------------------------------
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static const std::string defaultPlacer;
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static const std::vector<std::string> availablePlacers;
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static const std::string defaultRouter;
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static const std::vector<std::string> availableRouters;
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std::unordered_map<WireId, WireInfo> wires;
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std::unordered_map<BelId, BelInfo> bels;
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// WIP to link without failure
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std::unordered_set<PipId> all_pips;
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std::vector<PipId> empty_pip_list;
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std::vector<BelPin> empty_belpin_list;
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// Conversion between numbers and rnode types and IdString, for fast wire name implementation
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std::vector<IdString> int2id;
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std::unordered_map<IdString, int> id2int;
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std::vector<IdString> rn_t2id;
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std::unordered_map<IdString, CycloneV::rnode_type_t> id2rn_t;
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// This structure is only used for nextpnr-created wires
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std::unordered_map<IdStringList, WireId> npnr_wirebyname;
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};
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NEXTPNR_NAMESPACE_END
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#endif |