181 lines
8.3 KiB
Python
181 lines
8.3 KiB
Python
#
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# nextpnr -- Next Generation Place and Route
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#
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# Copyright (C) 2024 The Project Peppercorn Authors.
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#
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose with or without fee is hereby granted, provided that the above
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# copyright notice and this permission notice appear in all copies.
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#
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# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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#
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import os
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from os import path
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import sys
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import argparse
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sys.path.append(path.join(path.dirname(__file__), "../../.."))
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from himbaechel_dbgen.chip import *
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PIP_EXTRA_MUX = 1
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PIP_EXTRA_CPE = 2
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MUX_INVERT = 1
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MUX_VISIBLE = 2
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parser = argparse.ArgumentParser()
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parser.add_argument("--lib", help="Project Peppercorn python database script path", type=str, required=True)
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parser.add_argument("--device", help="name of device to export", type=str, required=True)
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parser.add_argument("--bba", help="bba file to write", type=str, required=True)
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args = parser.parse_args()
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sys.path.append(os.path.expanduser(args.lib))
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sys.path += args.lib
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import chip
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import die
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@dataclass
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class PipExtraData(BBAStruct):
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pip_type: int
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name: IdString
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bits: int = 0
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value: int = 0
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invert: int = 0
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def serialise_lists(self, context: str, bba: BBAWriter):
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pass
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def serialise(self, context: str, bba: BBAWriter):
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bba.u32(self.name.index)
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bba.u8(self.bits)
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bba.u8(self.value)
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bba.u8(self.invert)
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bba.u8(self.pip_type)
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def set_timings(ch):
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speed = "DEFAULT"
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tmg = ch.set_speed_grades([speed])
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def main():
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# Range needs to be +1, but we are adding +2 more to coordinates, since
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# they are starting from -2 instead of zero required for nextpnr
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dev = chip.get_device(args.device)
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ch = Chip("gatemate", args.device, dev.max_col() + 3, dev.max_row() + 3)
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# Init constant ids
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ch.strs.read_constids(path.join(path.dirname(__file__), "..", "constids.inc"))
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ch.read_gfxids(path.join(path.dirname(__file__), "..", "gfxids.inc"))
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for type_name in die.get_tile_type_list():
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tt = ch.create_tile_type(type_name)
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for group in die.get_groups_for_type(type_name):
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tt.create_group(group.name, group.type)
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for wire in die.get_endpoints_for_type(type_name):
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tt.create_wire(wire.name, wire.type)
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for prim in die.get_primitives_for_type(type_name):
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bel = tt.create_bel(prim.name, prim.type, prim.z)
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for pin in die.get_primitive_pins(prim.type):
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tt.add_bel_pin(bel, pin.name, f"{prim.name}.{pin.name}", pin.dir)
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for mux in die.get_mux_connections_for_type(type_name):
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pp = tt.create_pip(mux.src, mux.dst)
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mux_flags = MUX_INVERT if mux.invert else 0
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mux_flags |= MUX_VISIBLE if mux.visible else 0
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id(mux.name), mux.bits, mux.value, mux_flags)
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if "CPE" in type_name:
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pp = tt.create_pip("CPE.IN1", "CPE.RAM_O2")
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pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_O2"))
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if "GPIO" in type_name:
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tt.create_wire("GPIO.OUT_D1", "WIRE_INTERNAL")
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tt.create_wire("GPIO.OUT_D2", "WIRE_INTERNAL")
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#tt.create_wire("GPIO.OUT_Q1", "WIRE_INTERNAL")
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#tt.create_wire("GPIO.OUT_Q2", "WIRE_INTERNAL")
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#tt.create_wire("GPIO.OUT_CLK","WIRE_INTERNAL")
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#tt.create_wire("GPIO.CLK_INT","WIRE_INTERNAL")
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pp = tt.create_pip("GPIO.OUT1", "GPIO.OUT_D1")
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.OUT1_4"), 1, 0, MUX_VISIBLE)
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pp = tt.create_pip("GPIO.OUT4", "GPIO.OUT_D1")
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.OUT1_4"), 1, 1, MUX_VISIBLE)
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pp = tt.create_pip("GPIO.OUT2", "GPIO.OUT_D2")
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.OUT2_3"), 1, 0, MUX_VISIBLE)
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pp = tt.create_pip("GPIO.OUT3", "GPIO.OUT_D2")
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.OUT2_3"), 1, 1, MUX_VISIBLE)
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pp = tt.create_pip("GPIO.OUT_D1","GPIO.DO")
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.OUT23_14_SEL"), 1, 0, MUX_VISIBLE)
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pp = tt.create_pip("GPIO.OUT_D2","GPIO.DO")
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.OUT23_14_SEL"), 1, 1, MUX_VISIBLE)
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pp = tt.create_pip("GPIO.OUT2","GPIO.OE")
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.OE_SIGNAL"), 2, 1, MUX_VISIBLE)
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pp = tt.create_pip("GPIO.OUT3","GPIO.OE")
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.OE_SIGNAL"), 2, 2, MUX_VISIBLE)
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pp = tt.create_pip("GPIO.OUT4","GPIO.OE")
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.OE_SIGNAL"), 2, 3, MUX_VISIBLE)
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#pp = tt.create_pip("GPIO.OUT4", "GPIO.CLK_INT")
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#pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.CLK_1_4"), 1, 0, MUX_VISIBLE)
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#pp = tt.create_pip("GPIO.OUT1", "GPIO.CLK_INT")
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#pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.CLK_1_4"), 1, 1, MUX_VISIBLE)
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#pp = tt.create_pip("GPIO.CLK_INT", "GPIO.OUT_CLK")
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#pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.SEL_OUT_CLOCK"), 1, 1, MUX_VISIBLE)
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#pp = tt.create_pip("GPIO.CLOCK1", "GPIO.OUT_CLK")
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#pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.OUT_CLOCK"), 2, 0, MUX_VISIBLE)
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#pp = tt.create_pip("GPIO.CLOCK2", "GPIO.OUT_CLK")
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#pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.OUT_CLOCK"), 2, 1, MUX_VISIBLE)
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#pp = tt.create_pip("GPIO.CLOCK3", "GPIO.OUT_CLK")
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#pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.OUT_CLOCK"), 2, 2, MUX_VISIBLE)
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#pp = tt.create_pip("GPIO.CLOCK4", "GPIO.OUT_CLK")
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#pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.OUT_CLOCK"), 2, 3, MUX_VISIBLE)
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#tt.create_wire("GPIO.IN_D1", "WIRE_INTERNAL")
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#tt.create_wire("GPIO.IN_D2", "WIRE_INTERNAL")
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#tt.create_wire("GPIO.IN_Q1", "WIRE_INTERNAL")
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#tt.create_wire("GPIO.IN_Q2", "WIRE_INTERNAL")
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#tt.create_wire("GPIO.IN_CLK","WIRE_INTERNAL")
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#pp = tt.create_pip("GPIO.CLK_INT", "GPIO.IN_CLK")
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#pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.SEL_IN_CLOCK"), 1, 1, MUX_VISIBLE)
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#pp = tt.create_pip("GPIO.CLOCK1", "GPIO.IN_CLK")
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#pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.IN_CLOCK"), 2, 0, MUX_VISIBLE)
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#pp = tt.create_pip("GPIO.CLOCK2", "GPIO.IN_CLK")
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#pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.IN_CLOCK"), 2, 1, MUX_VISIBLE)
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#pp = tt.create_pip("GPIO.CLOCK3", "GPIO.IN_CLK")
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#pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.IN_CLOCK"), 2, 2, MUX_VISIBLE)
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#pp = tt.create_pip("GPIO.CLOCK4", "GPIO.IN_CLK")
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#pp.extra_data = PipExtraData(PIP_EXTRA_MUX,ch.strs.id("GPIO.IN_CLOCK"), 2, 3, MUX_VISIBLE)
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tt.create_pip("GPIO.DI", "GPIO.IN1")
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tt.create_pip("GPIO.DI", "GPIO.IN2")
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# Setup tile grid
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for x in range(dev.max_col() + 3):
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for y in range(dev.max_row() + 3):
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ch.set_tile_type(x, y, dev.get_tile_type(x - 2,y - 2))
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# Create nodes between tiles
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for _,nodes in dev.get_connections():
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node = []
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for conn in nodes:
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node.append(NodeWire(conn.x + 2, conn.y + 2, conn.name))
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ch.add_node(node)
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set_timings(ch)
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for package in dev.get_packages():
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pkg = ch.create_package(package)
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for pad in dev.get_package_pads(package):
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pkg.create_pad(pad.name, f"X{pad.x+2}Y{pad.y+2}", pad.bel, pad.function, pad.bank)
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ch.write_bba(args.bba)
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if __name__ == '__main__':
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main()
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