292 lines
11 KiB
C++
292 lines
11 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2018 David Shah <dave@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "bitstream.h"
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#include <vector>
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inline TileType tile_at(const Chip &chip, int x, int y)
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{
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return chip.chip_info.tile_grid[y * chip.chip_info.width + x];
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}
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const ConfigEntryPOD &find_config(const TileInfoPOD &tile,
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const std::string &name)
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{
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for (int i = 0; i < tile.num_config_entries; i++) {
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if (std::string(tile.entries[i].name) == name) {
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return tile.entries[i];
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}
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}
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assert(false);
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}
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std::tuple<int8_t, int8_t, int8_t> get_ieren(const BitstreamInfoPOD &bi,
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int8_t x, int8_t y, int8_t z)
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{
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for (int i = 0; i < bi.num_ierens; i++) {
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auto ie = bi.ierens[i];
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if (ie.iox == x && ie.ioy == y && ie.ioz == z) {
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return std::make_tuple(ie.ierx, ie.iery, ie.ierz);
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}
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}
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// No pin at this location
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return std::make_tuple(-1, -1, -1);
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};
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void set_config(const TileInfoPOD &ti, vector<vector<int8_t>> &tile_cfg,
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const std::string &name, bool value, int index = -1)
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{
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const ConfigEntryPOD &cfg = find_config(ti, name);
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if (index == -1) {
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for (int i = 0; i < cfg.num_bits; i++) {
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int8_t &cbit = tile_cfg.at(cfg.bits[i].row).at(cfg.bits[i].col);
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cbit = value;
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}
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} else {
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int8_t &cbit = tile_cfg.at(cfg.bits[index].row).at(cfg.bits[index].col);
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cbit = value;
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}
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}
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void write_asc(const Design &design, std::ostream &out)
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{
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const Chip &chip = design.chip;
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// [y][x][row][col]
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const ChipInfoPOD &ci = chip.chip_info;
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const BitstreamInfoPOD &bi = *ci.bits_info;
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std::vector<std::vector<std::vector<std::vector<int8_t>>>> config;
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config.resize(ci.height);
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for (int y = 0; y < ci.height; y++) {
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config.at(y).resize(ci.width);
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for (int x = 0; x < ci.width; x++) {
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TileType tile = tile_at(chip, x, y);
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int rows = bi.tiles_nonrouting[tile].rows;
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int cols = bi.tiles_nonrouting[tile].cols;
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config.at(y).at(x).resize(rows, vector<int8_t>(cols));
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}
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}
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out << ".comment from next-pnr" << std::endl;
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switch (chip.args.type) {
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case ChipArgs::LP384:
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out << ".device 384" << std::endl;
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break;
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case ChipArgs::HX1K:
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case ChipArgs::LP1K:
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out << ".device 1k" << std::endl;
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break;
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case ChipArgs::HX8K:
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case ChipArgs::LP8K:
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out << ".device 8k" << std::endl;
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break;
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case ChipArgs::UP5K:
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out << ".device 5k" << std::endl;
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break;
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default:
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assert(false);
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}
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// Set pips
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for (auto pip : chip.getPips()) {
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if (chip.pip_to_net[pip.index] != IdString()) {
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const PipInfoPOD &pi = ci.pip_data[pip.index];
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const SwitchInfoPOD &swi = bi.switches[pi.switch_index];
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for (int i = 0; i < swi.num_bits; i++) {
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bool val =
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(pi.switch_mask & (1 << ((swi.num_bits - 1) - i))) != 0;
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int8_t &cbit = config.at(swi.y)
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.at(swi.x)
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.at(swi.cbits[i].row)
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.at(swi.cbits[i].col);
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if (bool(cbit) != 0)
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assert(false);
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cbit = val;
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}
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}
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}
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// Set logic cell config
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for (auto cell : design.cells) {
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BelId bel = cell.second->bel;
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if (bel == BelId()) {
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std::cout << "Found unplaced cell " << cell.first
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<< " while generating bitstream!" << std::endl;
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continue;
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}
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const BelInfoPOD &beli = ci.bel_data[bel.index];
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int x = beli.x, y = beli.y, z = beli.z;
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if (cell.second->type == "ICESTORM_LC") {
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TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC];
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unsigned lut_init = std::stoi(cell.second->params["LUT_INIT"]);
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bool neg_clk = std::stoi(cell.second->params["NEG_CLK"]);
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bool dff_enable = std::stoi(cell.second->params["DFF_ENABLE"]);
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bool async_sr = std::stoi(cell.second->params["ASYNC_SR"]);
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bool set_noreset = std::stoi(cell.second->params["SET_NORESET"]);
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bool carry_enable = std::stoi(cell.second->params["CARRY_ENABLE"]);
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vector<bool> lc(20, false);
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// From arachne-pnr
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static std::vector<int> lut_perm = {
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4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0,
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};
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for (int i = 0; i < 16; i++) {
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if ((lut_init >> i) & 0x1)
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lc.at(lut_perm.at(i)) = true;
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}
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lc.at(8) = carry_enable;
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lc.at(9) = dff_enable;
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lc.at(18) = set_noreset;
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lc.at(19) = async_sr;
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for (int i = 0; i < 20; i++)
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set_config(ti, config.at(y).at(x), "LC_" + std::to_string(z),
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lc.at(i), i);
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set_config(ti, config.at(y).at(x), "NegClk", neg_clk);
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} else if (cell.second->type == "SB_IO") {
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TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
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unsigned pin_type = std::stoi(cell.second->params["PIN_TYPE"]);
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bool neg_trigger = std::stoi(cell.second->params["NEG_TRIGGER"]);
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bool pullup = std::stoi(cell.second->params["PULLUP"]);
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for (int i = 0; i < 6; i++) {
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bool val = (pin_type >> i) & 0x01;
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set_config(ti, config.at(y).at(x),
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"IOB_" + std::to_string(z) + ".PINTYPE_" +
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std::to_string(i),
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val);
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}
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auto ieren = get_ieren(bi, x, y, z);
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int iex, iey, iez;
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std::tie(iex, iey, iez) = ieren;
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assert(iez != -1);
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bool input_en = false;
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if ((chip.wire_to_net[chip.getWireBelPin(bel, PIN_D_IN_0).index] !=
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IdString()) ||
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(chip.wire_to_net[chip.getWireBelPin(bel, PIN_D_IN_1).index] !=
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IdString())) {
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input_en = true;
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}
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if(chip.args.type == ChipArgs::LP1K || chip.args.type == ChipArgs::HX1K) {
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set_config(ti, config.at(iey).at(iex),
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"IoCtrl.IE_" + std::to_string(iez), !input_en);
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set_config(ti, config.at(iey).at(iex),
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"IoCtrl.REN_" + std::to_string(iez), !pullup);
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} else {
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set_config(ti, config.at(iey).at(iex),
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"IoCtrl.IE_" + std::to_string(iez), input_en);
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set_config(ti, config.at(iey).at(iex),
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"IoCtrl.REN_" + std::to_string(iez), !pullup);
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}
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} else if (cell.second->type == "SB_GB") {
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// no cell config bits
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} else {
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assert(false);
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}
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}
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// Set config bits in unused IO
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for (auto bel : chip.getBels()) {
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if (chip.bel_to_cell[bel.index] == IdString() && chip.getBelType(bel) == TYPE_SB_IO) {
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TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
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const BelInfoPOD &beli = ci.bel_data[bel.index];
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int x = beli.x, y = beli.y, z = beli.z;
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auto ieren = get_ieren(bi, x, y, z);
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int iex, iey, iez;
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std::tie(iex, iey, iez) = ieren;
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if (iez != -1) {
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if(chip.args.type == ChipArgs::LP1K || chip.args.type == ChipArgs::HX1K) {
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set_config(ti, config.at(iey).at(iex),
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"IoCtrl.IE_" + std::to_string(iez), true);
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set_config(ti, config.at(iey).at(iex),
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"IoCtrl.REN_" + std::to_string(iez), false);
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}
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}
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}
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}
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// Set other config bits
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for (int y = 0; y < ci.height; y++) {
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for (int x = 0; x < ci.width; x++) {
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TileType tile = tile_at(chip, x, y);
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TileInfoPOD &ti = bi.tiles_nonrouting[tile];
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// disable RAM to stop icebox_vlog crashing (FIXME)
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if ((tile == TILE_RAMB) && (chip.args.type == ChipArgs::LP1K || chip.args.type == ChipArgs::HX1K)) {
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set_config(ti, config.at(y).at(x), "RamConfig.PowerUp", true);
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}
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// set all ColBufCtrl bits (FIXME)
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bool setColBufCtrl = true;
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if (chip.args.type == ChipArgs::LP1K || chip.args.type == ChipArgs::HX1K) {
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if (tile == TILE_RAMB || tile == TILE_RAMT) {
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setColBufCtrl = (y == 3 || y == 5 || y == 11 || y == 13);
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} else {
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setColBufCtrl = (y == 4 || y == 5 || y == 12 || y == 13);
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}
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} else if (chip.args.type == ChipArgs::LP8K || chip.args.type == ChipArgs::HX8K) {
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setColBufCtrl = (y == 8 || y == 9 || y == 24 || y == 25);
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}
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if (setColBufCtrl) {
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set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_0", true);
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set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_1", true);
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set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_2", true);
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set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_3", true);
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set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_4", true);
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set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_5", true);
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set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_6", true);
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set_config(ti, config.at(y).at(x), "ColBufCtrl.glb_netwk_7", true);
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}
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}
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}
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// Write config out
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for (int y = 0; y < ci.height; y++) {
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for (int x = 0; x < ci.width; x++) {
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TileType tile = tile_at(chip, x, y);
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if (tile == TILE_NONE)
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continue;
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switch (tile) {
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case TILE_LOGIC:
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out << ".logic_tile";
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break;
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case TILE_IO:
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out << ".io_tile";
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break;
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case TILE_RAMB:
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out << ".ramb_tile";
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break;
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case TILE_RAMT:
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out << ".ramt_tile";
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break;
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default:
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assert(false);
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}
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out << " " << x << " " << y << std::endl;
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for (auto row : config.at(y).at(x)) {
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for (auto col : row) {
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if (col == 1)
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out << "1";
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else
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out << "0";
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}
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out << std::endl;
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}
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out << std::endl;
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}
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}
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}
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