478 lines
16 KiB
Python
478 lines
16 KiB
Python
#!/usr/bin/env python3
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import sys
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import re
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dev_name = None
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dev_width = None
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dev_height = None
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num_wires = None
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tiles = dict()
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wire_uphill = dict()
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wire_downhill = dict()
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pip_xy = dict()
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bel_name = list()
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bel_type = list()
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bel_pos = list()
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bel_wires = list()
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switches = list()
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ierens = list()
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wire_uphill_belport = dict()
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wire_downhill_belports = dict()
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wire_names = dict()
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wire_names_r = dict()
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wire_xy = dict()
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num_tile_types = 5
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tile_sizes = {_: (0, 0) for _ in range(num_tile_types)}
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tile_bits = [[] for _ in range(num_tile_types)]
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cbit_re = re.compile(r'B(\d+)\[(\d+)\]')
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def maj_wire_name(name):
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if re.match(r"lutff_\d/(in|out)", name[2]):
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return True
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return False
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def cmp_wire_names(newname, oldname):
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if maj_wire_name(newname):
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return True
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if maj_wire_name(oldname):
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return False
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return newname < oldname
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with open(sys.argv[1], "r") as f:
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mode = None
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for line in f:
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line = line.split()
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if len(line) == 0 or line[0] == "#":
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continue
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if line[0] == ".device":
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dev_name = line[1]
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dev_width = int(line[2])
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dev_height = int(line[3])
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num_wires = int(line[4])
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continue
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if line[0] == ".net":
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mode = ("net", int(line[1]))
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continue
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if line[0] == ".buffer":
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mode = ("buffer", int(line[3]), int(line[1]), int(line[2]))
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switches.append((line[3], int(line[1]), int(line[2]), line[4:]))
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continue
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if line[0] == ".routing":
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mode = ("routing", int(line[3]), int(line[1]), int(line[2]))
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switches.append((line[3], int(line[1]), int(line[2]), line[4:]))
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continue
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if line[0] == ".io_tile":
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tiles[(int(line[1]), int(line[2]))] = "io"
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mode = None
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continue
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if line[0] == ".logic_tile":
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tiles[(int(line[1]), int(line[2]))] = "logic"
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mode = None
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continue
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if line[0] == ".ramb_tile":
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tiles[(int(line[1]), int(line[2]))] = "ramb"
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mode = None
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continue
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if line[0] == ".ramt_tile":
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tiles[(int(line[1]), int(line[2]))] = "ramt"
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mode = None
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continue
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if line[0] == ".logic_tile_bits":
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mode = ("bits", 1)
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tile_sizes[1] = (int(line[1]), int(line[2]))
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continue
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if line[0] == ".io_tile_bits":
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mode = ("bits", 2)
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tile_sizes[2] = (int(line[1]), int(line[2]))
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continue
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if line[0] == ".ramb_tile_bits":
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mode = ("bits", 3)
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tile_sizes[3] = (int(line[1]), int(line[2]))
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continue
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if line[0] == ".ramt_tile_bits":
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mode = ("bits", 4)
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tile_sizes[4] = (int(line[1]), int(line[2]))
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continue
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if line[0] == ".ieren":
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mode = ("ieren",)
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continue
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if (line[0][0] == ".") or (mode is None):
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mode = None
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continue
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if mode[0] == "net":
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wname = (int(line[0]), int(line[1]), line[2])
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wire_names[wname] = mode[1]
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if (mode[1] not in wire_names_r) or cmp_wire_names(wname, wire_names_r[mode[1]]):
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wire_names_r[mode[1]] = wname
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if mode[1] not in wire_xy:
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wire_xy[mode[1]] = list()
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wire_xy[mode[1]].append((int(line[0]), int(line[1])))
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continue
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if mode[0] == "buffer":
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wire_a = int(line[1])
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wire_b = mode[1]
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if wire_a not in wire_downhill:
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wire_downhill[wire_a] = set()
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if wire_b not in wire_uphill:
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wire_uphill[wire_b] = set()
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wire_downhill[wire_a].add(wire_b)
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wire_uphill[wire_b].add(wire_a)
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pip_xy[(wire_a, wire_b)] = (mode[2], mode[3], int(line[0], 2), len(switches) - 1)
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continue
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if mode[0] == "routing":
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wire_a = int(line[1])
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wire_b = mode[1]
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if wire_a not in wire_downhill:
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wire_downhill[wire_a] = set()
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if wire_b not in wire_uphill:
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wire_uphill[wire_b] = set()
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wire_downhill[wire_a].add(wire_b)
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wire_uphill[wire_b].add(wire_a)
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pip_xy[(wire_a, wire_b)] = (mode[2], mode[3], int(line[0], 2), len(switches) - 1)
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if wire_b not in wire_downhill:
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wire_downhill[wire_b] = set()
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if wire_a not in wire_uphill:
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wire_uphill[wire_a] = set()
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wire_downhill[wire_b].add(wire_a)
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wire_uphill[wire_a].add(wire_b)
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pip_xy[(wire_b, wire_a)] = (mode[2], mode[3], int(line[0], 2), len(switches) - 1)
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continue
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if mode[0] == "bits":
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name = line[0]
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bits = []
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for b in line[1:]:
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m = cbit_re.match(b)
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assert m
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bits.append((int(m.group(1)), int(m.group(2))))
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tile_bits[mode[1]].append((name, bits))
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if mode[0] == "ieren":
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ierens.append(tuple([int(_) for _ in line]))
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def add_bel_input(bel, wire, port):
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if wire not in wire_downhill_belports:
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wire_downhill_belports[wire] = set()
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wire_downhill_belports[wire].add((bel, port))
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bel_wires[bel].append((wire, port))
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def add_bel_output(bel, wire, port):
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assert wire not in wire_uphill_belport
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wire_uphill_belport[wire] = (bel, port)
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bel_wires[bel].append((wire, port))
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def add_bel_lc(x, y, z):
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bel = len(bel_name)
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bel_name.append("%d_%d_lc%d" % (x, y, z))
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bel_type.append("ICESTORM_LC")
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bel_pos.append((x, y, z))
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bel_wires.append(list())
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wire_cen = wire_names[(x, y, "lutff_global/cen")]
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wire_clk = wire_names[(x, y, "lutff_global/clk")]
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wire_s_r = wire_names[(x, y, "lutff_global/s_r")]
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if z == 0:
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wire_cin = wire_names[(x, y, "carry_in_mux")]
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else:
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wire_cin = wire_names[(x, y, "lutff_%d/cout" % (z-1))]
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wire_in_0 = wire_names[(x, y, "lutff_%d/in_0" % z)]
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wire_in_1 = wire_names[(x, y, "lutff_%d/in_1" % z)]
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wire_in_2 = wire_names[(x, y, "lutff_%d/in_2" % z)]
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wire_in_3 = wire_names[(x, y, "lutff_%d/in_3" % z)]
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wire_out = wire_names[(x, y, "lutff_%d/out" % z)]
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wire_cout = wire_names[(x, y, "lutff_%d/cout" % z)]
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wire_lout = wire_names[(x, y, "lutff_%d/lout" % z)] if z < 7 else None
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add_bel_input(bel, wire_cen, "CEN")
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add_bel_input(bel, wire_clk, "CLK")
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add_bel_input(bel, wire_s_r, "SR")
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add_bel_input(bel, wire_cin, "CIN")
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add_bel_input(bel, wire_in_0, "I0")
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add_bel_input(bel, wire_in_1, "I1")
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add_bel_input(bel, wire_in_2, "I2")
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add_bel_input(bel, wire_in_3, "I3")
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add_bel_output(bel, wire_out, "O")
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add_bel_output(bel, wire_cout, "COUT")
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if wire_lout is not None:
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add_bel_output(bel, wire_lout, "LO")
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def add_bel_io(x, y, z):
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bel = len(bel_name)
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bel_name.append("%d_%d_io%d" % (x, y, z))
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bel_type.append("SB_IO")
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bel_pos.append((x, y, z))
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bel_wires.append(list())
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wire_cen = wire_names[(x, y, "io_global/cen")]
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wire_iclk = wire_names[(x, y, "io_global/inclk")]
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wire_oclk = wire_names[(x, y, "io_global/latch")]
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wire_latch = wire_names[(x, y, "io_global/outclk")]
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wire_din_0 = wire_names[(x, y, "io_%d/D_IN_0" % z)]
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wire_din_1 = wire_names[(x, y, "io_%d/D_IN_1" % z)]
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wire_dout_0 = wire_names[(x, y, "io_%d/D_OUT_0" % z)]
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wire_dout_1 = wire_names[(x, y, "io_%d/D_OUT_1" % z)]
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wire_out_en = wire_names[(x, y, "io_%d/OUT_ENB" % z)]
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add_bel_input(bel, wire_cen, "CLOCK_ENABLE")
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add_bel_input(bel, wire_iclk, "INPUT_CLK")
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add_bel_input(bel, wire_oclk, "OUTPUT_CLK")
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add_bel_input(bel, wire_latch, "LATCH_INPUT_VALUE")
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add_bel_output(bel, wire_din_0, "D_IN_0")
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add_bel_output(bel, wire_din_1, "D_IN_1")
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add_bel_input(bel, wire_dout_0, "D_OUT_0")
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add_bel_input(bel, wire_dout_1, "D_OUT_1")
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add_bel_input(bel, wire_out_en, "OUTPUT_ENABLE")
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def add_bel_ram(x, y):
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bel = len(bel_name)
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bel_name.append("%d_%d_ram" % (x, y))
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bel_type.append("ICESTORM_RAM")
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bel_pos.append((x, y, 0))
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bel_wires.append(list())
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if (x, y, "ram/WE") in wire_names:
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# iCE40 1K-style memories
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y0, y1 = y, y+1
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else:
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# iCE40 8K-style memories
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y1, y0 = y, y+1
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for i in range(16):
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add_bel_input (bel, wire_names[(x, y0 if i < 8 else y1, "ram/MASK_%d" % i)], "MASK_%d" % i)
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add_bel_input (bel, wire_names[(x, y0 if i < 8 else y1, "ram/WDATA_%d" % i)], "WDATA_%d" % i)
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add_bel_output(bel, wire_names[(x, y0 if i < 8 else y1, "ram/RDATA_%d" % i)], "RDATA_%d" % i)
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for i in range(11):
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add_bel_input(bel, wire_names[(x, y0, "ram/WADDR_%d" % i)], "WADDR_%d" % i)
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add_bel_input(bel, wire_names[(x, y1, "ram/RADDR_%d" % i)], "RADDR_%d" % i)
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add_bel_input(bel, wire_names[(x, y0, "ram/WCLK")], "WCLK")
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add_bel_input(bel, wire_names[(x, y0, "ram/WCLKE")], "WCLKE")
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add_bel_input(bel, wire_names[(x, y0, "ram/WE")], "WE")
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add_bel_input(bel, wire_names[(x, y1, "ram/RCLK")], "RCLK")
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add_bel_input(bel, wire_names[(x, y1, "ram/RCLKE")], "RCLKE")
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add_bel_input(bel, wire_names[(x, y1, "ram/RE")], "RE")
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def add_bel_gb(x, y, g):
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bel = len(bel_name)
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bel_name.append("%d_%d_gb" % (x, y))
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bel_type.append("SB_GB")
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bel_pos.append((x, y, 0))
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bel_wires.append(list())
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add_bel_input(bel, wire_names[(x, y, "fabout")], "USER_SIGNAL_TO_GLOBAL_BUFFER")
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add_bel_output(bel, wire_names[(x, y, "glb_netwk_%d" % g)], "GLOBAL_BUFFER_OUTPUT")
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for tile_xy, tile_type in sorted(tiles.items()):
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if tile_type == "logic":
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for i in range(8):
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add_bel_lc(tile_xy[0], tile_xy[1], i)
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if tile_type == "io":
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for i in range(2):
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add_bel_io(tile_xy[0], tile_xy[1], i)
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if tile_type == "ramb":
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add_bel_ram(tile_xy[0], tile_xy[1])
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if dev_name == "1k":
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add_bel_gb( 7, 0, 0)
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add_bel_gb( 7, 17, 1)
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add_bel_gb(13, 9, 2)
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add_bel_gb( 0, 9, 3)
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add_bel_gb( 6, 17, 4)
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add_bel_gb( 6, 0, 5)
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add_bel_gb( 0, 8, 6)
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add_bel_gb(13, 8, 7)
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print('#include "chip.h"')
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for bel in range(len(bel_name)):
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print("static BelWirePOD bel_wires_%d[%d] = {" % (bel, len(bel_wires[bel])))
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for i in range(len(bel_wires[bel])):
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print(" {%d, PIN_%s}%s" % (bel_wires[bel][i] + ("," if i+1 < len(bel_wires[bel]) else "",)))
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print("};")
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print("BelInfoPOD bel_data_%s[%d] = {" % (dev_name, len(bel_name)))
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for bel in range(len(bel_name)):
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print(" {\"%s\", TYPE_%s, %d, bel_wires_%d, %d, %d, %d}%s" % (bel_name[bel], bel_type[bel],
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len(bel_wires[bel]), bel, bel_pos[bel][0], bel_pos[bel][1], bel_pos[bel][2],
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"," if bel+1 < len(bel_name) else ""))
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print("};")
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wireinfo = list()
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pipinfo = list()
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pipcache = dict()
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for wire in range(num_wires):
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if wire in wire_uphill:
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pips = list()
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for src in wire_uphill[wire]:
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if (src, wire) not in pipcache:
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pipcache[(src, wire)] = len(pipinfo)
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pipinfo.append(" {%d, %d, 1.0, %d, %d, %d, %d}" % (src, wire, pip_xy[(src, wire)][0], pip_xy[(src, wire)][1], pip_xy[(src, wire)][2], pip_xy[(src, wire)][3]))
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pips.append("%d" % pipcache[(src, wire)])
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num_uphill = len(pips)
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list_uphill = "wire%d_uppips" % wire
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print("static int wire%d_uppips[] = {%s};" % (wire, ", ".join(pips)))
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else:
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num_uphill = 0
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list_uphill = "nullptr"
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if wire in wire_downhill:
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pips = list()
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for dst in wire_downhill[wire]:
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if (wire, dst) not in pipcache:
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pipcache[(wire, dst)] = len(pipinfo)
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pipinfo.append(" {%d, %d, 1.0, %d, %d, %d, %d}" % (wire, dst, pip_xy[(wire, dst)][0], pip_xy[(wire, dst)][1], pip_xy[(wire, dst)][2], pip_xy[(wire, dst)][3]))
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pips.append("%d" % pipcache[(wire, dst)])
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num_downhill = len(pips)
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list_downhill = "wire%d_downpips" % wire
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print("static int wire%d_downpips[] = {%s};" % (wire, ", ".join(pips)))
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else:
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num_downhill = 0
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list_downhill = "nullptr"
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if wire in wire_downhill_belports:
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num_bels_downhill = len(wire_downhill_belports[wire])
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print("static BelPortPOD wire%d_downbels[] = {" % wire)
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print(",\n".join([" {%d, PIN_%s}" % it for it in wire_downhill_belports[wire]]))
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print("};")
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else:
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num_bels_downhill = 0
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info = " {"
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info += "\"%d_%d_%s\", " % wire_names_r[wire]
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info += "%d, %d, %s, %s, %d, " % (num_uphill, num_downhill, list_uphill, list_downhill, num_bels_downhill)
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if wire in wire_uphill_belport:
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info += "{%d, PIN_%s}, " % wire_uphill_belport[wire]
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else:
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info += "{-1, PIN_NONE}, "
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info += ("wire%d_downbels, " % wire) if num_bels_downhill > 0 else "nullptr, "
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avg_x, avg_y = 0, 0
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if wire in wire_xy:
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for x, y in wire_xy[wire]:
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avg_x += x
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avg_y += y
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avg_x /= len(wire_xy[wire])
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avg_y /= len(wire_xy[wire])
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info += "%f, %f}" % (avg_x, avg_y)
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wireinfo.append(info)
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tilegrid = []
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for y in range(dev_height):
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for x in range(dev_width):
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if (x, y) in tiles:
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tilegrid.append("TILE_%s" % (tiles[x, y].upper()))
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else:
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tilegrid.append("TILE_NONE")
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tileinfo = []
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for t in range(num_tile_types):
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centries_info = []
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for cb in tile_bits[t]:
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name, bits = cb
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safename = re.sub("[^A-Za-z0-9]", "_", name)
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bits_list = ["{%d, %d}" % _ for _ in bits]
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print("static ConfigBitPOD tile%d_%s_bits[%d] = {%s};" % (t, safename, len(bits_list), ", ".join(bits_list)))
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centries_info.append('{"%s", %d, tile%d_%s_bits}' % (name, len(bits_list), t, safename))
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print("static ConfigEntryPOD tile%d_config[%d] = {" % (t, len(centries_info)))
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print(",\n".join(centries_info))
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print("};")
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tileinfo.append("{%d, %d, %d, tile%d_config}" % (tile_sizes[t][0], tile_sizes[t][1], len(centries_info), t))
|
|
|
|
switchinfo = []
|
|
switchid = 0
|
|
for switch in switches:
|
|
dst, x, y, bits = switch
|
|
bitlist = []
|
|
for b in bits:
|
|
m = cbit_re.match(b)
|
|
assert m
|
|
bitlist.append("{%d, %d}" % (int(m.group(1)), int(m.group(2))))
|
|
cbits = ", ".join(bitlist)
|
|
switchinfo.append("{%d, %d, %d, {%s}}" % (x, y, len(bits), cbits))
|
|
switchid += 1
|
|
|
|
iereninfo = []
|
|
for ieren in ierens:
|
|
iereninfo.append("{%d, %d, %d, %d, %d, %d}" % ieren)
|
|
|
|
print("static WireInfoPOD wire_data_%s[%d] = {" % (dev_name, num_wires))
|
|
print(",\n".join(wireinfo))
|
|
print("};")
|
|
|
|
print("static PipInfoPOD pip_data_%s[%d] = {" % (dev_name, len(pipinfo)))
|
|
print(",\n".join(pipinfo))
|
|
print("};")
|
|
|
|
print("static SwitchInfoPOD switch_data_%s[%d] = {" % (dev_name, len(switchinfo)))
|
|
print(",\n".join(switchinfo))
|
|
print("};")
|
|
|
|
print("static TileInfoPOD tile_data_%s[%d] = {" % (dev_name, num_tile_types))
|
|
print(",\n".join(tileinfo))
|
|
print("};")
|
|
|
|
print("static IerenInfoPOD ieren_data_%s[%d] = {" % (dev_name, len(iereninfo)))
|
|
print(",\n".join(iereninfo))
|
|
print("};")
|
|
|
|
|
|
print("static BitstreamInfoPOD bits_info_%s = {" % dev_name)
|
|
print("%d, %d, tile_data_%s, switch_data_%s, ieren_data_%s" % (len(switchinfo), len(iereninfo), dev_name, dev_name, dev_name))
|
|
print("};")
|
|
|
|
print("static TileType tile_grid_%s[%d] = {" % (dev_name, len(tilegrid)))
|
|
print(",\n".join(tilegrid))
|
|
print("};")
|
|
|
|
print("ChipInfoPOD chip_info_%s = {" % dev_name)
|
|
print(" %d, %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo), len(switchinfo)))
|
|
print(" bel_data_%s, wire_data_%s, pip_data_%s," % (dev_name, dev_name, dev_name))
|
|
print(" tile_grid_%s, &bits_info_%s" % (dev_name, dev_name))
|
|
print("};")
|