64 lines
2.0 KiB
Verilog
64 lines
2.0 KiB
Verilog
module top(input clk_pin, output [3:0] led_pin, output gpio0_pin);
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wire clk;
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wire [7:0] led;
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wire gpio0;
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(* BEL="X0/Y35/PIOA" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("INPUT")) clk_buf (.B(clk_pin), .O(clk));
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(* BEL="X0/Y23/PIOC" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf_0 (.B(led_pin[0]), .I(led[0]));
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(* BEL="X0/Y23/PIOD" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf_1 (.B(led_pin[1]), .I(led[1]));
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(* BEL="X0/Y26/PIOA" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf_2 (.B(led_pin[2]), .I(led[2]));
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(* BEL="X0/Y26/PIOC" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf_3 (.B(led_pin[3]), .I(led[3]));
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(* BEL="X0/Y26/PIOB" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf_4 (.B(led_pin[4]), .I(led[4]));
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(* BEL="X0/Y32/PIOD" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf_5 (.B(led_pin[5]), .I(led[5]));
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(* BEL="X0/Y26/PIOD" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf_6 (.B(led_pin[6]), .I(led[6]));
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(* BEL="X0/Y29/PIOD" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf_7 (.B(led_pin[7]), .I(led[7]));
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(* BEL="X0/Y62/PIOD" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) gpio0_buf (.B(gpio0_pin), .I(gpio0));
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localparam ctr_width = 28;
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reg [ctr_width-1:0] ctr = 0;
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always@(posedge clk)
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ctr <= ctr + 1'b1;
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reg [9:0] brightness [0:7];
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reg [7:0] led_reg;
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genvar i;
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generate
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for (i = 0; i < 8; i=i+1) begin
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always @ (posedge clk) begin
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if (ctr[ctr_width-1 : ctr_width-3] > i)
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brightness[i] <= 10'h3FF;
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else if (ctr[ctr_width-1 : ctr_width-3] == i)
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brightness[i] <= ctr[ctr_width-4:ctr_width-13];
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else
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brightness[i] <= 0;
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led_reg[i] <= ctr[9:0] < brightness[i];
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end
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end
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endgenerate
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assign led = led_reg;
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// Tie GPIO0, keep board from rebooting
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TRELLIS_SLICE #(.MODE("LOGIC"), .LUT0_INITVAL(16'hFFFF)) vcc (.F0(gpio0));
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endmodule
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