25 lines
591 B
Tcl
25 lines
591 B
Tcl
# Usage
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# tcl synth_generic.tcl {K} {out.json}
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set LUT_K 4
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if {$argc > 0} { set LUT_K [lindex $argv 0] }
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yosys read_verilog -lib [file dirname [file normalize $argv0]]/prims.v
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yosys hierarchy -check
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yosys proc
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yosys flatten
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yosys tribuf -logic
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yosys deminout
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yosys synth -run coarse
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yosys memory_map
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yosys opt -full
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yosys techmap -map +/techmap.v
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yosys opt -fast
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yosys abc -lut $LUT_K -dress
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yosys clean
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yosys techmap -D LUT_K=$LUT_K -map [file dirname [file normalize $argv0]]/cells_map.v
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yosys clean
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yosys hierarchy -check
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yosys stat
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if {$argc > 1} { yosys write_json [lindex $argv 1] }
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