500 lines
14 KiB
C++
500 lines
14 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef NEXTPNR_H
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#error Include "arch.h" via "nextpnr.h" only.
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#endif
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NEXTPNR_NAMESPACE_BEGIN
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/**** Everything in this section must be kept in sync with chipdb.py ****/
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template <typename T> struct RelPtr
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{
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int32_t offset;
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// void set(const T *ptr) {
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// offset = reinterpret_cast<const char*>(ptr) -
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// reinterpret_cast<const char*>(this);
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// }
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const T *get() const { return reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset); }
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const T &operator[](size_t index) const { return get()[index]; }
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const T &operator*() const { return *(get()); }
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const T *operator->() const { return get(); }
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};
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// FIXME: All "rel locs" are actually absolute, naming typo in facade_import.
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// Does not affect runtime functionality.
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NPNR_PACKED_STRUCT(struct BelWirePOD {
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LocationPOD rel_wire_loc;
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int32_t wire_index;
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int32_t port;
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int32_t dir;
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});
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NPNR_PACKED_STRUCT(struct BelInfoPOD {
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RelPtr<char> name;
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int32_t type;
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int32_t z;
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int32_t num_bel_wires;
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RelPtr<BelWirePOD> bel_wires;
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});
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NPNR_PACKED_STRUCT(struct PipLocatorPOD {
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LocationPOD rel_loc;
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int32_t index;
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});
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NPNR_PACKED_STRUCT(struct BelPortPOD {
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LocationPOD rel_bel_loc;
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int32_t bel_index;
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int32_t port;
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});
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NPNR_PACKED_STRUCT(struct PipInfoPOD {
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LocationPOD src;
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LocationPOD dst;
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int32_t src_idx;
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int32_t dst_idx;
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int32_t timing_class;
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int16_t tile_type;
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int8_t pip_type;
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int8_t padding;
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});
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NPNR_PACKED_STRUCT(struct WireInfoPOD {
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RelPtr<char> name;
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int32_t tile_wire;
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int32_t num_uphill;
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int32_t num_downhill;
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RelPtr<PipLocatorPOD> pips_uphill;
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RelPtr<PipLocatorPOD> pips_downhill;
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int32_t num_bel_pins;
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RelPtr<BelPortPOD> bel_pins;
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});
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NPNR_PACKED_STRUCT(struct TileTypePOD {
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int32_t num_bels;
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int32_t num_wires;
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int32_t num_pips;
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RelPtr<BelInfoPOD> bel_data;
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RelPtr<WireInfoPOD> wire_data;
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RelPtr<PipInfoPOD> pips_data;
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});
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NPNR_PACKED_STRUCT(struct PackagePinPOD {
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RelPtr<char> name;
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LocationPOD abs_loc;
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int32_t bel_index;
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});
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NPNR_PACKED_STRUCT(struct PackageInfoPOD {
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RelPtr<char> name;
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int32_t num_pins;
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RelPtr<PackagePinPOD> pin_data;
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});
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NPNR_PACKED_STRUCT(struct PIOInfoPOD {
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LocationPOD abs_loc;
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int32_t bel_index;
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RelPtr<char> function_name;
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int16_t bank;
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int16_t dqsgroup;
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});
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NPNR_PACKED_STRUCT(struct TileNamePOD {
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RelPtr<char> name;
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int16_t type_idx;
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int16_t padding;
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});
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NPNR_PACKED_STRUCT(struct TileInfoPOD {
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int32_t num_tiles;
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RelPtr<TileNamePOD> tile_names;
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});
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NPNR_PACKED_STRUCT(struct ChipInfoPOD {
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int32_t width, height;
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int32_t num_tiles;
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int32_t num_packages, num_pios;
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int32_t const_id_count;
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RelPtr<TileTypePOD> tiles;
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RelPtr<RelPtr<char>> tiletype_names;
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RelPtr<PackageInfoPOD> package_info;
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RelPtr<PIOInfoPOD> pio_info;
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RelPtr<TileInfoPOD> tile_info;
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});
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/************************ End of chipdb section. ************************/
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// Iterators
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struct BelIterator
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{
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const ChipInfoPOD *chip;
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int cursor_index;
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int cursor_tile;
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BelIterator operator++()
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{
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cursor_index++;
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while (cursor_tile < chip->num_tiles &&
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cursor_index >= chip->tiles[cursor_tile].num_bels) {
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cursor_index = 0;
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cursor_tile++;
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}
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return *this;
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}
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BelIterator operator++(int)
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{
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BelIterator prior(*this);
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++(*this);
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return prior;
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}
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bool operator!=(const BelIterator &other) const
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{
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return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile;
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}
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bool operator==(const BelIterator &other) const
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{
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return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile;
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}
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BelId operator*() const
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{
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BelId ret;
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ret.location.x = cursor_tile % chip->width;
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ret.location.y = cursor_tile / chip->width;
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ret.index = cursor_index;
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return ret;
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}
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};
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struct BelRange
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{
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BelIterator b, e;
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BelIterator begin() const { return b; }
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BelIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct ArchArgs
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{
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enum ArchArgsTypes
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{
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NONE,
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LCMXO2_256HC,
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LCMXO2_640HC,
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LCMXO2_1200HC,
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LCMXO2_2000HC,
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LCMXO2_4000HC,
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LCMXO2_7000HC,
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} type = NONE;
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std::string package;
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enum SpeedGrade
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{
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SPEED_1 = 0,
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SPEED_2,
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SPEED_3,
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SPEED_4,
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SPEED_5,
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SPEED_6,
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} speed = SPEED_4;
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};
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struct WireInfo;
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struct PipInfo
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{
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IdString name, type;
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std::map<IdString, std::string> attrs;
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NetInfo *bound_net;
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WireId srcWire, dstWire;
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DelayInfo delay;
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DecalXY decalxy;
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Loc loc;
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};
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struct WireInfo
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{
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IdString name, type;
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std::map<IdString, std::string> attrs;
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NetInfo *bound_net;
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std::vector<PipId> downhill, uphill, aliases;
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BelPin uphill_bel_pin;
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std::vector<BelPin> downhill_bel_pins;
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std::vector<BelPin> bel_pins;
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DecalXY decalxy;
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int x, y;
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};
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struct PinInfo
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{
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IdString name;
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WireId wire;
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PortType type;
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};
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struct BelInfo
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{
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IdString name, type;
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std::map<IdString, std::string> attrs;
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CellInfo *bound_cell;
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std::unordered_map<IdString, PinInfo> pins;
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DecalXY decalxy;
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int x, y, z;
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bool gb;
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};
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struct GroupInfo
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{
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IdString name;
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std::vector<BelId> bels;
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std::vector<WireId> wires;
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std::vector<PipId> pips;
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std::vector<GroupId> groups;
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DecalXY decalxy;
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};
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struct CellDelayKey
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{
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IdString from, to;
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inline bool operator==(const CellDelayKey &other) const { return from == other.from && to == other.to; }
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};
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NEXTPNR_NAMESPACE_END
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namespace std {
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template <> struct hash<NEXTPNR_NAMESPACE_PREFIX CellDelayKey>
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{
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std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX CellDelayKey &dk) const noexcept
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{
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std::size_t seed = std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.from);
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seed ^= std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.to) + 0x9e3779b9 + (seed << 6) + (seed >> 2);
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return seed;
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}
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};
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} // namespace std
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NEXTPNR_NAMESPACE_BEGIN
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struct CellTiming
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{
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std::unordered_map<IdString, TimingPortClass> portClasses;
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std::unordered_map<CellDelayKey, DelayInfo> combDelays;
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std::unordered_map<IdString, std::vector<TimingClockingInfo>> clockingInfo;
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};
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struct Arch : BaseCtx
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{
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const ChipInfoPOD *chip_info;
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const PackageInfoPOD *package_info;
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// Placeholders to be removed.
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std::unordered_map<Loc, BelId> bel_by_loc;
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std::vector<BelId> bel_id_dummy;
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std::vector<BelPin> bel_pin_dummy;
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std::vector<WireId> wire_id_dummy;
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std::vector<PipId> pip_id_dummy;
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std::vector<GroupId> group_id_dummy;
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std::vector<GraphicElement> graphic_element_dummy;
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std::map<IdString, std::string> attrs_dummy;
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// Helpers
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template <typename Id> const TileTypePOD *tileInfo(Id &id) const
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{
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return &(chip_info->tiles[id.location.y * chip_info->width + id.location.x]);
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}
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// ---------------------------------------------------------------
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// Common Arch API. Every arch must provide the following methods.
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ArchArgs args;
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Arch(ArchArgs args);
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static bool isAvailable(ArchArgs::ArchArgsTypes chip);
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std::string getChipName() const;
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IdString archId() const { return id("machxo2"); }
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ArchArgs archArgs() const { return args; }
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IdString archArgsToId(ArchArgs args) const;
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static const int max_loc_bels = 20;
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int getGridDimX() const { return chip_info->width; }
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int getGridDimY() const { return chip_info->height; }
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int getTileBelDimZ(int x, int y) const { return max_loc_bels; }
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// TODO: Make more precise? The CENTER MUX having config bits across
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// tiles can complicate this?
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int getTilePipDimZ(int x, int y) const { return 2; }
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BelId getBelByName(IdString name) const;
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IdString getBelName(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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std::stringstream name;
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name << "X" << bel.location.x << "/Y" << bel.location.y << "/" << tileInfo(bel)->bel_data[bel.index].name.get();
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return id(name.str());
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}
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Loc getBelLocation(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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Loc loc;
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loc.x = bel.location.x;
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loc.y = bel.location.y;
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loc.z = tileInfo(bel)->bel_data[bel.index].z;
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return loc;
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}
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BelId getBelByLocation(Loc loc) const;
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const std::vector<BelId> &getBelsByTile(int x, int y) const;
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bool getBelGlobalBuf(BelId bel) const;
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uint32_t getBelChecksum(BelId bel) const;
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void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength);
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void unbindBel(BelId bel);
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bool checkBelAvail(BelId bel) const;
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CellInfo *getBoundBelCell(BelId bel) const;
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CellInfo *getConflictingBelCell(BelId bel) const;
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BelRange getBels() const
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{
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BelRange range;
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range.b.cursor_tile = 0;
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range.b.cursor_index = -1;
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range.b.chip = chip_info;
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++range.b; //-1 and then ++ deals with the case of no Bels in the first tile
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range.e.cursor_tile = chip_info->width * chip_info->height;
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range.e.cursor_index = 0;
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range.e.chip = chip_info;
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return range;
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}
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IdString getBelType(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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IdString id;
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id.index = tileInfo(bel)->bel_data[bel.index].type;
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return id;
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}
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const std::map<IdString, std::string> &getBelAttrs(BelId bel) const;
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WireId getBelPinWire(BelId bel, IdString pin) const;
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PortType getBelPinType(BelId bel, IdString pin) const;
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std::vector<IdString> getBelPins(BelId bel) const;
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WireId getWireByName(IdString name) const;
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IdString getWireName(WireId wire) const;
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IdString getWireType(WireId wire) const;
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const std::map<IdString, std::string> &getWireAttrs(WireId wire) const;
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uint32_t getWireChecksum(WireId wire) const;
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void bindWire(WireId wire, NetInfo *net, PlaceStrength strength);
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void unbindWire(WireId wire);
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bool checkWireAvail(WireId wire) const;
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NetInfo *getBoundWireNet(WireId wire) const;
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WireId getConflictingWireWire(WireId wire) const { return wire; }
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NetInfo *getConflictingWireNet(WireId wire) const;
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DelayInfo getWireDelay(WireId wire) const { return DelayInfo(); }
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const std::vector<WireId> &getWires() const;
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const std::vector<BelPin> &getWireBelPins(WireId wire) const;
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PipId getPipByName(IdString name) const;
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IdString getPipName(PipId pip) const;
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IdString getPipType(PipId pip) const;
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const std::map<IdString, std::string> &getPipAttrs(PipId pip) const;
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uint32_t getPipChecksum(PipId pip) const;
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void bindPip(PipId pip, NetInfo *net, PlaceStrength strength);
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void unbindPip(PipId pip);
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bool checkPipAvail(PipId pip) const;
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NetInfo *getBoundPipNet(PipId pip) const;
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WireId getConflictingPipWire(PipId pip) const;
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NetInfo *getConflictingPipNet(PipId pip) const;
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const std::vector<PipId> &getPips() const;
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Loc getPipLocation(PipId pip) const;
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WireId getPipSrcWire(PipId pip) const;
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WireId getPipDstWire(PipId pip) const;
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DelayInfo getPipDelay(PipId pip) const;
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const std::vector<PipId> &getPipsDownhill(WireId wire) const;
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const std::vector<PipId> &getPipsUphill(WireId wire) const;
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const std::vector<PipId> &getWireAliases(WireId wire) const;
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GroupId getGroupByName(IdString name) const;
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IdString getGroupName(GroupId group) const;
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std::vector<GroupId> getGroups() const;
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const std::vector<BelId> &getGroupBels(GroupId group) const;
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const std::vector<WireId> &getGroupWires(GroupId group) const;
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const std::vector<PipId> &getGroupPips(GroupId group) const;
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const std::vector<GroupId> &getGroupGroups(GroupId group) const;
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delay_t estimateDelay(WireId src, WireId dst) const;
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delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
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delay_t getDelayEpsilon() const { return 0.001; }
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delay_t getRipupDelayPenalty() const { return 0.015; }
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float getDelayNS(delay_t v) const { return v; }
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DelayInfo getDelayFromNS(float ns) const
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{
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DelayInfo del;
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del.delay = ns;
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return del;
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}
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uint32_t getDelayChecksum(delay_t v) const { return 0; }
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bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const;
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ArcBounds getRouteBoundingBox(WireId src, WireId dst) const;
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bool pack();
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bool place();
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bool route();
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const std::vector<GraphicElement> &getDecalGraphics(DecalId decal) const;
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DecalXY getBelDecal(BelId bel) const;
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DecalXY getWireDecal(WireId wire) const;
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DecalXY getPipDecal(PipId pip) const;
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DecalXY getGroupDecal(GroupId group) const;
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bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
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// Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
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TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const;
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// Get the TimingClockingInfo of a port
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TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const;
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bool isValidBelForCell(CellInfo *cell, BelId bel) const;
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bool isBelLocationValid(BelId bel) const;
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static const std::string defaultPlacer;
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static const std::vector<std::string> availablePlacers;
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static const std::string defaultRouter;
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static const std::vector<std::string> availableRouters;
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// ---------------------------------------------------------------
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// Internal usage
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void assignArchInfo();
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bool cellsCompatible(const CellInfo **cells, int count) const;
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};
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NEXTPNR_NAMESPACE_END
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