414 lines
7.9 KiB
C++
414 lines
7.9 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "design.h"
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#ifndef CHIP_H
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#define CHIP_H
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struct DelayInfo
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{
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float delay = 0;
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float raiseDelay() { return delay; }
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float fallDelay() { return delay; }
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};
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// -----------------------------------------------------------------------
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enum BelType
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{
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TYPE_NIL,
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TYPE_ICESTORM_LC,
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TYPE_SB_IO
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};
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IdString belTypeToId(BelType type);
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BelType belTypeFromId(IdString id);
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enum PortPin
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{
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PIN_NIL,
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PIN_IN_0,
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PIN_IN_1,
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PIN_IN_2,
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PIN_IN_3,
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PIN_O,
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PIN_LO,
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PIN_CIN,
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PIN_COUT,
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PIN_CEN,
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PIN_CLK,
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PIN_SR,
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PIN_PACKAGE_PIN,
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PIN_LATCH_INPUT_VALUE,
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PIN_CLOCK_ENABLE,
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PIN_INPUT_CLK,
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PIN_OUTPUT_CLK,
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PIN_OUTPUT_ENABLE,
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PIN_D_OUT_0,
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PIN_D_OUT_1,
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PIN_D_IN_0,
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PIN_D_IN_1
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};
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IdString PortPinToId(PortPin type);
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PortPin PortPinFromId(IdString id);
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// -----------------------------------------------------------------------
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struct BelInfoPOD
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{
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const char *name;
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BelType type;
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};
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struct WireDelayPOD
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{
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int32_t wire_index;
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float delay;
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};
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struct BelPortPOD
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{
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int32_t bel_index;
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PortPin port;
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};
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struct WireInfoPOD
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{
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const char *name;
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int num_uphill, num_downhill, num_bidir;
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WireDelayPOD *wires_uphill, *wires_downhill, *wires_bidir;
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int num_bels_downhill;
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BelPortPOD bel_uphill;
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BelPortPOD *bels_downhill;
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};
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extern int num_bels_384;
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extern int num_bels_1k;
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extern int num_bels_5k;
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extern int num_bels_8k;
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extern BelInfoPOD bel_data_384[];
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extern BelInfoPOD bel_data_1k[];
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extern BelInfoPOD bel_data_5k[];
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extern BelInfoPOD bel_data_8k[];
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extern int num_wires_384;
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extern int num_wires_1k;
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extern int num_wires_5k;
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extern int num_wires_8k;
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extern WireInfoPOD wire_data_384[];
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extern WireInfoPOD wire_data_1k[];
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extern WireInfoPOD wire_data_5k[];
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extern WireInfoPOD wire_data_8k[];
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// -----------------------------------------------------------------------
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struct BelId
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{
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int32_t index = -1;
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bool nil() const {
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return index < 0;
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}
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};
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struct WireId
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{
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int32_t index = -1;
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bool nil() const {
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return index < 0;
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}
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};
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namespace std
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{
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template<> struct hash<BelId>
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{
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std::size_t operator()(const BelId &bel) const noexcept
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{
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return bel.index;
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}
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};
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template<> struct hash<WireId>
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{
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std::size_t operator()(const WireId &wire) const noexcept
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{
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return wire.index;
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}
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};
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}
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// -----------------------------------------------------------------------
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struct BelIterator
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{
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int cursor;
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void operator++() { cursor++; }
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bool operator!=(const BelIterator &other) const { return cursor != other.cursor; }
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BelId operator*() const {
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BelId ret;
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ret.index = cursor;
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return ret;
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}
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};
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struct BelRange
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{
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BelIterator b, e;
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BelIterator begin() const { return b; }
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BelIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct AllWireIterator
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{
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int cursor;
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void operator++() { cursor++; }
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bool operator!=(const AllWireIterator &other) const { return cursor != other.cursor; }
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WireId operator*() const {
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WireId ret;
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ret.index = cursor;
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return ret;
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}
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};
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struct AllWireRange
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{
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AllWireIterator b, e;
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AllWireIterator begin() const { return b; }
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AllWireIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct WireDelay
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{
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WireId wire;
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DelayInfo delay;
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};
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struct WireDelayIterator
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{
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WireDelayPOD *ptr = nullptr;
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void operator++() { ptr++; }
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bool operator!=(const WireDelayIterator &other) const { return ptr != other.ptr; }
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WireDelay operator*() const {
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WireDelay ret;
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ret.wire.index = ptr->wire_index;
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ret.delay.delay = ptr->delay;
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return ret;
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}
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};
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struct WireDelayRange
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{
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WireDelayIterator b, e;
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WireDelayIterator begin() const { return b; }
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WireDelayIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct BelPin
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{
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BelId bel;
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PortPin pin;
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};
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struct BelPinIterator
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{
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BelPortPOD *ptr = nullptr;
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void operator++() { ptr++; }
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bool operator!=(const BelPinIterator &other) const { return ptr != other.ptr; }
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BelPin operator*() const {
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BelPin ret;
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ret.bel.index = ptr->bel_index;
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ret.pin = ptr->port;
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return ret;
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}
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};
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struct BelPinRange
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{
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BelPinIterator b, e;
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BelPinIterator begin() const { return b; }
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BelPinIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct GuiLine
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{
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float x1, y1, x2, y2;
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};
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struct ChipArgs
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{
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enum {
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NONE,
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LP384,
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LP1K,
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LP8K,
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HX1K,
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HX8K,
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UP5K
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} type = NONE;
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};
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struct Chip
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{
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int num_bels, num_wires;
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BelInfoPOD *bel_data;
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WireInfoPOD *wire_data;
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mutable dict<IdString, int> wire_by_name;
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mutable dict<IdString, int> bel_by_name;
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Chip(ChipArgs args);
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void setBelActive(BelId, bool) { }
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bool getBelActive(BelId) { return true; }
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BelId getBelByName(IdString name) const;
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WireId getWireByName(IdString name) const;
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IdString getBelName(BelId bel) const
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{
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return bel_data[bel.index].name;
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}
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IdString getWireName(WireId wire) const
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{
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return wire_data[wire.index].name;
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}
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BelRange getBels() const
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{
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BelRange range;
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range.b.cursor = 0;
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range.e.cursor = num_bels;
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return range;
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}
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BelRange getBelsByType(BelType type) const
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{
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BelRange range;
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// FIXME
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#if 0
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if (type == "TYPE_A") {
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range.b.cursor = bels_type_a_begin;
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range.e.cursor = bels_type_a_end;
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}
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...
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#endif
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return range;
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}
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BelType getBelType(BelId bel) const
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{
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return bel_data[bel.index].type;
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}
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// FIXME: void getBelPosition(BelId bel, float &x, float &y) const;
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// FIXME: void getWirePosition(WireId wire, float &x, float &y) const;
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// FIXME: vector<GuiLine> getBelGuiLines(BelId bel) const;
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// FIXME: vector<GuiLine> getWireGuiLines(WireId wire) const;
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AllWireRange getWires() const
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{
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AllWireRange range;
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range.b.cursor = 0;
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range.e.cursor = num_wires;
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return range;
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}
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WireDelayRange getWiresUphill(WireId wire) const
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{
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WireDelayRange range;
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range.b.ptr = wire_data[wire.index].wires_uphill;
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range.e.ptr = wire_data[wire.index].wires_uphill + wire_data[wire.index].num_uphill;
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return range;
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}
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WireDelayRange getWiresDownhill(WireId wire) const
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{
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WireDelayRange range;
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range.b.ptr = wire_data[wire.index].wires_downhill;
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range.e.ptr = wire_data[wire.index].wires_downhill + wire_data[wire.index].num_downhill;
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return range;
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}
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WireDelayRange getWiresBidir(WireId wire) const
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{
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WireDelayRange range;
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range.b.ptr = wire_data[wire.index].wires_bidir;
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range.e.ptr = wire_data[wire.index].wires_bidir + wire_data[wire.index].num_bidir;
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return range;
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}
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WireDelayRange getWireAliases(WireId wire) const
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{
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WireDelayRange range;
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return range;
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}
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WireId getWireBelPin(BelId bel, PortPin pin) const;
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BelPin getBelPinUphill(WireId wire) const
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{
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BelPin ret;
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if (wire_data[wire.index].bel_uphill.bel_index >= 0) {
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ret.bel.index = wire_data[wire.index].bel_uphill.bel_index;
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ret.pin = wire_data[wire.index].bel_uphill.port;
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}
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return ret;
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}
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BelPinRange getBelPinsDownhill(WireId wire) const
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{
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BelPinRange range;
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range.b.ptr = wire_data[wire.index].bels_downhill;
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range.e.ptr = wire_data[wire.index].bels_downhill + wire_data[wire.index].num_bels_downhill;
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return range;
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}
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};
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#endif
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