23 lines
484 B
Verilog
23 lines
484 B
Verilog
module top(output LED1, LED2, LED3, LED4, LED5);
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localparam N = 31;
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wire [N:0] x;
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assign x[0] = x[N];
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genvar ii;
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generate
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for (ii = 0; ii < N; ii = ii + 1) begin
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(* ringosc *)
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SB_LUT4 #(.LUT_INIT(1)) lut_i(.I0(x[ii]), .I1(), .I2(), .I3(), .O(x[ii+1]));
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end
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endgenerate
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assign clk = x[N];
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reg [19:0] ctr;
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always @(posedge clk)
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ctr <= ctr + 1'b1;
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assign {LED5, LED4, LED3, LED2, LED1} = ctr[19:15];
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endmodule
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