18 lines
468 B
Verilog
18 lines
468 B
Verilog
module top(input clk, rst, output [7:0] leds);
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// TODO: Test miter circuit without reset value. SAT and SMT diverge without
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// reset value (SAT succeeds, SMT fails). I haven't figured out the correct
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// init set of options to make SAT fail.
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// "sat -verify -prove-asserts -set-init-def -seq 1 miter" causes assertion
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// failure in yosys.
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reg [7:0] ctr = 8'h00;
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always @(posedge clk)
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if (rst)
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ctr <= 8'h00;
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else
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ctr <= ctr + 1'b1;
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assign leds = ctr;
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endmodule
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