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6a1212a1e1
nextpnr/gowin
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YRabbit 6a1212a1e1 gowin: Add PLL support for the GW1NR-9 chip 
And also unified the fixing of PLL to bels: the point is that PLL being
at a certain location has the possibility to use a direct implicit wire
to the clock source, but once we decide to use this direct wire, the PLL
can no longer be moved.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-01-30 12:49:57 +10:00
..
arch_pybindings.cc Fixing old emails and names in copyrights 2021-06-12 13:22:38 +01:00
arch_pybindings.h Fixing old emails and names in copyrights 2021-06-12 13:22:38 +01:00
arch.cc gowin: Add PLL support for the GW1NR-9 chip 2023-01-30 12:49:57 +10:00
arch.h gowin: Add PLL support for the GW1NR-9 chip 2023-01-30 12:49:57 +10:00
archdefs.h gowin: add support for wide LUTs. 2021-10-07 18:38:33 +10:00
cells.cc gowin: Add PLL support for the GW1NR-9C chip 2023-01-26 20:26:05 +10:00
cells.h gowin: Add PLL support for the GW1NR-9C chip 2023-01-26 20:26:05 +10:00
CMakeLists.txt gowin: Add GW1NZ-1 2022-02-15 14:12:16 +02:00
constids.inc gowin: Add PLL support for the GW1NR-9C chip 2023-01-26 20:26:05 +10:00
cst.cc gowin: Add GUI. 2022-01-29 14:45:17 +10:00
cst.h gowin: Add GUI. 2022-01-29 14:45:17 +10:00
family.cmake Gowin target (#542) 2020-12-30 14:59:55 +00:00
gfx.cc gowin: fix build for wasm 2022-12-21 16:13:08 +10:00
gfx.h gowin: fix build for wasm 2022-12-21 16:13:08 +10:00
globals.cc gowin: Add PLL support for the GW1NR-9C chip 2023-01-26 20:26:05 +10:00
globals.h gowin: improve clock wire routing 2022-12-30 11:55:39 +10:00
main.cc gowin: improve clock wire routing 2022-12-30 11:55:39 +10:00
pack.cc gowin: Add PLL support for the GW1NR-9 chip 2023-01-30 12:49:57 +10:00