c13b34f20e
The following primitives are implemented for the GW1N-1, GW2A-18,
GW2AR-18C, GW1NSR-4C, GW1NR-9C, GW1NR-9 and GW1N-4 chips:
* pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9 - read only memory - (bitwidth: 9, 18, 36).
* SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B - semidual port - (bitwidth: 9, 18, 36).
* DPB - dual port - (bitwidth: 16).
* DPX9B - dual port - (bitwidth: 18).
* SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9 - single port - (bitwidth: 9, 18, 36).
For GW1NSR-4C and GW1NR-9 chips, SP/SPX9 primitives with data widths
of 32/36 bits are implemented using a pair of 16-bit wide
primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
52 lines
1.2 KiB
C++
52 lines
1.2 KiB
C++
#ifndef GOWIN_UTILS_H
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#define GOWIN_UTILS_H
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#include "idstringlist.h"
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#include "nextpnr_namespaces.h"
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#include "nextpnr_types.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace BelFlags {
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static constexpr uint32_t FLAG_SIMPLE_IO = 0x100;
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}
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struct GowinUtils
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{
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Context *ctx;
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GowinUtils() {}
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void init(Context *ctx) { this->ctx = ctx; }
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// tile
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IdString get_tile_class(int x, int y);
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Loc get_tile_io16_offs(int x, int y);
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// pin functions: GCLKT_4, SSPI_CS, READY etc
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IdStringList get_pin_funcs(BelId bel);
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// Bels and pips
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bool is_simple_io_bel(BelId bel);
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Loc get_pair_iologic_bel(Loc loc);
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BelId get_io_bel_from_iologic(BelId bel);
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bool is_diff_io_supported(IdString type);
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bool have_bottom_io_cnds(void);
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IdString get_bottom_io_wire_a_net(int8_t condition);
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IdString get_bottom_io_wire_b_net(int8_t condition);
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// wires
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inline bool is_wire_type_default(IdString wire_type) { return wire_type == IdString(); }
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// chip dependent
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bool have_SP32(void);
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// make cell but do not include it in the list of chip cells.
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std::unique_ptr<CellInfo> create_cell(IdString name, IdString type);
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};
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NEXTPNR_NAMESPACE_END
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#endif
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