.. | ||
.gitignore | ||
blinky_ext.v | ||
blinky_tb.v | ||
blinky.v | ||
demo.sh | ||
mitertest.sh | ||
README.md | ||
rgbcount.v | ||
simple.sh | ||
simtest.sh | ||
tinyfpga.v | ||
uart.v |
MachXO2 Architecture Example
This directory contains a simple example of running nextpnr-machxo2
:
-
simple.sh
produces nextpnr output in the files{pack,place,pnr}*.json
, as well as pre-pnr and post-pnr diagrams in{pack,place,pnr}*.{dot, png}
. -
simtest.sh
will useyosys
to generate a Verilog file from{pack,place,pnr}blinky.json
, called{pack,place,pnr}blinky.v
. It will then and compare{pack,place,pnr}blinky.v
's simulation behavior to the original verilog file (blinky.v
) using theiverilog
compiler andvvp
runtime. This is known as post-place-and-route simulation. -
mitertest.sh
is similar tosimtest.sh
, but more comprehensive. This script creates a miter circuit to compare the output port values of{pack,place,pnr}*.v
against the original Verilog code when both modules are fed the same values on their input ports.All possible inputs and resulting outputs can be tested in reasonable time by using
yosys
' built-in SAT solver orz3
, an external SMT solver. -
demo.sh
creates bitstreams for TinyFPGA Ax and writes the resulting bitstream to MachXO2's internal flash usingtinyproga
.
As nextpnr-machxo2
is developed the contents simple.sh
, simtest.sh
,
mitertest.sh
, and demo.sh
are subject to change.
How To Run
The following applies to all sh
scripts except demo.sh
.
Each sh
script runs yosys and nextpnr to validate a blinky design in various
ways. The mode
argument to each script- pack
, place
, or pnr
- stop
nextpnr-machxo2
after the specified phase and writes out a JSON file of the
results in {pack,place,pnr}blinky.json
; pnr
runs all of the Pack, Place,
and Route phases.
mitertest.sh
requires an additional option- sat
or smt
- to choose between
verifying the miter with either yosys' built-in SAT solver, or an external
SMT solver.
In principle, mitertest.sh
should work in sat
or smt
mode with all
example Verilog files which don't use the internal oscillator (OSCH) or other
hard IP. However, as of this writing, only blinky.v
passes correctly for a
few reasons:
-
The sim models for MachXO2 primitives used by the
gate
module containinitial
values by design, as it matches chip behavior. Without any of the following in thegold
module (likeblinky_ext.v
currently):- An external reset signal
- Internal power-on reset signal (e.g.
reg int_rst = 1'd1;
) initial
values to manually set registers
the
gold
andgate
modules will inherently not match.Examples using an internal power-on reset (e.g.
uart.v
) also have issues that I haven't debugged yet in bothsat
andsmt
mode. -
To keep the
gold
/gate
generation simpler, examples are currently assumed to not instantiate MachXO2 simulation primitives directly (FACADE_IO
,FACADE_FF
, etc). -
synth_machxo2
runsdeminout
oninouts
when generating thegate
module. This is not handled yet when generating thegold
module.
To keep file count lower, all yosys scripts are written inline inside the
sh
scripts using the -p
option.
demo.sh
requires a prefix that matches one of the self-contained Verilog
examples in this directory. For instance, to create a bitstream from
tinyfpga.v
, use demo.sh tinyfpga
. The script will catch Verilog files which
are not meant to be programmed onto TinyFPA Ax.
Clean
To clean output files from all scripts, run:
rm -rf *.dot *.json *.png *.vcd *.smt2 *.log *.txt *.bit {pack,place,pnr}*.v blinky_simtest*
Verilog Examples
-
blinky.v
/blinky_tb.v
- A blinky example meant for simulation. -
tinyfpga.v
- Blink the LED on TinyFPA Ax. -
rgbcount.v
- Blink an RGB LED using TinyFPGA Ax, more closely-based on the TinyFPGA Ax guide. -
blinky_ext.v
- Blink the LED on TinyFPA Ax using an external pin (pin 6). -
uart.v
- UART loopback demo at 19200 baud. Requires the following pins:- Pin 1- RX LED
- Pin 2- TX (will echo RX)
- Pin 3- RX
- Pin 4- TX LED
- Pin 5- Load LED
- Pin 6- 12 MHz clock input
- Pin 7- Take LED
- Pin 8- Empty LED
Environment Variables For Scripts
YOSYS
- Set to the location of theyosys
binary to test. Defaults to theyosys
on the path. You may want to set this to ayosys
binary in your source tree if doing development.NEXTPNR
- Set to the location of thenextpnr-machxo2
binary to test. Defaults to thenextpnr-machxo2
binary at the root of thenextpnr
source tree. This should be set, for instance, if doing an out-of-tree build ofnextpnr-machxo2
.CELLS_SIM
- Set to the location ofmachxo2/cells_sim.v
simulation models. Defaults to whateveryosys-config
associated with the aboveYOSYS
binary returns. You may want to set this to/path/to/yosys/src/share/machxo2/cells_sim.v
if doing development;yosys-config
cannot find these "before-installation" simulation models.TRELLIS_DB
- Set to the location of the Project Trellis database to use. Defaults to nothing, which meansecppack
will use whatever database is on its path.