c13b34f20e
The following primitives are implemented for the GW1N-1, GW2A-18,
GW2AR-18C, GW1NSR-4C, GW1NR-9C, GW1NR-9 and GW1N-4 chips:
* pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9 - read only memory - (bitwidth: 9, 18, 36).
* SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B - semidual port - (bitwidth: 9, 18, 36).
* DPB - dual port - (bitwidth: 16).
* DPX9B - dual port - (bitwidth: 18).
* SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9 - single port - (bitwidth: 9, 18, 36).
For GW1NSR-4C and GW1NR-9 chips, SP/SPX9 primitives with data widths
of 32/36 bits are implemented using a pair of 16-bit wide
primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
108 lines
3.3 KiB
C++
108 lines
3.3 KiB
C++
#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
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#include "himbaechel_constids.h"
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#include "himbaechel_helpers.h"
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#include "gowin.h"
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#include "gowin_utils.h"
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NEXTPNR_NAMESPACE_BEGIN
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// tile extra data
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IdString GowinUtils::get_tile_class(int x, int y)
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{
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int tile = tile_by_xy(ctx->chip_info, x, y);
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const Tile_extra_data_POD *extra =
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reinterpret_cast<const Tile_extra_data_POD *>(chip_tile_info(ctx->chip_info, tile).extra_data.get());
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return IdString(extra->class_id);
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}
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// oser16/ides16 aux cell offsets
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Loc GowinUtils::get_tile_io16_offs(int x, int y)
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{
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int tile = tile_by_xy(ctx->chip_info, x, y);
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const Tile_extra_data_POD *extra =
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reinterpret_cast<const Tile_extra_data_POD *>(chip_tile_info(ctx->chip_info, tile).extra_data.get());
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return Loc(extra->io16_x_off, extra->io16_y_off, 0);
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}
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// pin functions: GCLKT_4, SSPI_CS, READY etc
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IdStringList GowinUtils::get_pin_funcs(BelId bel)
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{
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IdStringList bel_name = ctx->getBelName(bel);
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const PadInfoPOD *pins = ctx->package_info->pads.get();
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size_t len = ctx->package_info->pads.ssize();
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for (size_t i = 0; i < len; i++) {
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const PadInfoPOD *pin = &pins[i];
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if (IdString(pin->tile) == bel_name[0] && IdString(pin->bel) == bel_name[1]) {
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return IdStringList::parse(ctx, IdString(pin->pad_function).str(ctx));
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}
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}
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return IdStringList();
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}
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bool GowinUtils::is_simple_io_bel(BelId bel)
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{
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return chip_bel_info(ctx->chip_info, bel).flags & BelFlags::FLAG_SIMPLE_IO;
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}
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Loc GowinUtils::get_pair_iologic_bel(Loc loc)
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{
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loc.z = BelZ::IOLOGICA_Z + (1 - (loc.z - BelZ::IOLOGICA_Z));
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return loc;
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}
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BelId GowinUtils::get_io_bel_from_iologic(BelId bel)
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{
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Loc loc = ctx->getBelLocation(bel);
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loc.z = BelZ::IOBA_Z + loc.z - BelZ::IOLOGICA_Z;
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return ctx->getBelByLocation(loc);
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}
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bool GowinUtils::is_diff_io_supported(IdString type)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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for (auto &dtype : extra->diff_io_types) {
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if (IdString(dtype) == type) {
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return true;
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}
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}
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return false;
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}
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bool GowinUtils::have_bottom_io_cnds(void)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return extra->bottom_io.conditions.size() != 0;
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}
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IdString GowinUtils::get_bottom_io_wire_a_net(int8_t condition)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return IdString(extra->bottom_io.conditions[condition].wire_a_net);
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}
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IdString GowinUtils::get_bottom_io_wire_b_net(int8_t condition)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return IdString(extra->bottom_io.conditions[condition].wire_b_net);
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}
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bool GowinUtils::have_SP32(void)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return extra->chip_flags & Extra_chip_data_POD::HAS_SP32;
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}
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std::unique_ptr<CellInfo> GowinUtils::create_cell(IdString name, IdString type)
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{
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NPNR_ASSERT(!ctx->cells.count(name));
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return std::make_unique<CellInfo>(ctx, name, type);
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}
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NEXTPNR_NAMESPACE_END
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