77ffdd7fd4
Also move all tests in a tests directory Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
12 lines
153 B
Verilog
12 lines
153 B
Verilog
module top(input clk, input d, input r, output reg q);
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
if(r)
|
|
q <= 1'b0;
|
|
else
|
|
q <= d;
|
|
end
|
|
|
|
endmodule
|