b18ea204c2
It has not actually been implemented in any router for over 2.5 years and causes nothing more than confusion. It can always be added back if it forms part of a future solution; possibly as part of a more general database structure rethink. Signed-off-by: David Shah <dave@ds0.me>
301 lines
11 KiB
C++
301 lines
11 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef NEXTPNR_H
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#error Include "arch.h" via "nextpnr.h" only.
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#endif
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NEXTPNR_NAMESPACE_BEGIN
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struct ArchArgs
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{
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// Number of LUT inputs
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int K = 4;
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// y = mx + c relationship between distance and delay for interconnect
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// delay estimates
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double delayScale = 0.1, delayOffset = 0;
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};
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struct WireInfo;
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struct PipInfo
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{
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IdString name, type;
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std::map<IdString, std::string> attrs;
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NetInfo *bound_net;
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WireId srcWire, dstWire;
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DelayInfo delay;
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DecalXY decalxy;
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Loc loc;
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};
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struct WireInfo
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{
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IdString name, type;
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std::map<IdString, std::string> attrs;
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NetInfo *bound_net;
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std::vector<PipId> downhill, uphill;
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BelPin uphill_bel_pin;
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std::vector<BelPin> downhill_bel_pins;
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std::vector<BelPin> bel_pins;
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DecalXY decalxy;
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int x, y;
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};
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struct PinInfo
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{
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IdString name;
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WireId wire;
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PortType type;
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};
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struct BelInfo
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{
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IdString name, type;
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std::map<IdString, std::string> attrs;
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CellInfo *bound_cell;
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std::unordered_map<IdString, PinInfo> pins;
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DecalXY decalxy;
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int x, y, z;
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bool gb;
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};
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struct GroupInfo
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{
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IdString name;
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std::vector<BelId> bels;
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std::vector<WireId> wires;
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std::vector<PipId> pips;
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std::vector<GroupId> groups;
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DecalXY decalxy;
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};
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struct CellDelayKey
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{
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IdString from, to;
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inline bool operator==(const CellDelayKey &other) const { return from == other.from && to == other.to; }
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};
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NEXTPNR_NAMESPACE_END
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namespace std {
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template <> struct hash<NEXTPNR_NAMESPACE_PREFIX CellDelayKey>
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{
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std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX CellDelayKey &dk) const noexcept
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{
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std::size_t seed = std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.from);
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seed ^= std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.to) + 0x9e3779b9 + (seed << 6) + (seed >> 2);
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return seed;
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}
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};
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} // namespace std
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NEXTPNR_NAMESPACE_BEGIN
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struct CellTiming
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{
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std::unordered_map<IdString, TimingPortClass> portClasses;
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std::unordered_map<CellDelayKey, DelayInfo> combDelays;
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std::unordered_map<IdString, std::vector<TimingClockingInfo>> clockingInfo;
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};
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struct Arch : BaseCtx
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{
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std::string chipName;
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std::unordered_map<IdString, WireInfo> wires;
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std::unordered_map<IdString, PipInfo> pips;
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std::unordered_map<IdString, BelInfo> bels;
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std::unordered_map<GroupId, GroupInfo> groups;
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// These functions include useful errors if not found
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WireInfo &wire_info(IdString wire);
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PipInfo &pip_info(IdString wire);
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BelInfo &bel_info(IdString wire);
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std::vector<IdString> bel_ids, wire_ids, pip_ids;
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std::unordered_map<Loc, BelId> bel_by_loc;
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std::vector<std::vector<std::vector<BelId>>> bels_by_tile;
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std::unordered_map<DecalId, std::vector<GraphicElement>> decal_graphics;
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int gridDimX, gridDimY;
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std::vector<std::vector<int>> tileBelDimZ;
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std::vector<std::vector<int>> tilePipDimZ;
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std::unordered_map<IdString, CellTiming> cellTiming;
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void addWire(IdString name, IdString type, int x, int y);
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void addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc);
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void addBel(IdString name, IdString type, Loc loc, bool gb);
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void addBelInput(IdString bel, IdString name, IdString wire);
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void addBelOutput(IdString bel, IdString name, IdString wire);
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void addBelInout(IdString bel, IdString name, IdString wire);
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void addGroupBel(IdString group, IdString bel);
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void addGroupWire(IdString group, IdString wire);
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void addGroupPip(IdString group, IdString pip);
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void addGroupGroup(IdString group, IdString grp);
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void addDecalGraphic(DecalId decal, const GraphicElement &graphic);
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void setWireDecal(WireId wire, DecalXY decalxy);
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void setPipDecal(PipId pip, DecalXY decalxy);
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void setBelDecal(BelId bel, DecalXY decalxy);
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void setGroupDecal(GroupId group, DecalXY decalxy);
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void setWireAttr(IdString wire, IdString key, const std::string &value);
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void setPipAttr(IdString pip, IdString key, const std::string &value);
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void setBelAttr(IdString bel, IdString key, const std::string &value);
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void setLutK(int K);
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void setDelayScaling(double scale, double offset);
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void addCellTimingClock(IdString cell, IdString port);
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void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay);
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void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold);
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void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq);
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// ---------------------------------------------------------------
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// Common Arch API. Every arch must provide the following methods.
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ArchArgs args;
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Arch(ArchArgs args);
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std::string getChipName() const { return chipName; }
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IdString archId() const { return id("generic"); }
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ArchArgs archArgs() const { return args; }
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IdString archArgsToId(ArchArgs args) const { return id("none"); }
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int getGridDimX() const { return gridDimX; }
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int getGridDimY() const { return gridDimY; }
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int getTileBelDimZ(int x, int y) const { return tileBelDimZ[x][y]; }
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int getTilePipDimZ(int x, int y) const { return tilePipDimZ[x][y]; }
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BelId getBelByName(IdString name) const;
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IdString getBelName(BelId bel) const;
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Loc getBelLocation(BelId bel) const;
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BelId getBelByLocation(Loc loc) const;
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const std::vector<BelId> &getBelsByTile(int x, int y) const;
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bool getBelGlobalBuf(BelId bel) const;
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uint32_t getBelChecksum(BelId bel) const;
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void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength);
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void unbindBel(BelId bel);
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bool checkBelAvail(BelId bel) const;
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CellInfo *getBoundBelCell(BelId bel) const;
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CellInfo *getConflictingBelCell(BelId bel) const;
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const std::vector<BelId> &getBels() const;
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IdString getBelType(BelId bel) const;
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const std::map<IdString, std::string> &getBelAttrs(BelId bel) const;
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WireId getBelPinWire(BelId bel, IdString pin) const;
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PortType getBelPinType(BelId bel, IdString pin) const;
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std::vector<IdString> getBelPins(BelId bel) const;
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WireId getWireByName(IdString name) const;
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IdString getWireName(WireId wire) const;
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IdString getWireType(WireId wire) const;
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const std::map<IdString, std::string> &getWireAttrs(WireId wire) const;
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uint32_t getWireChecksum(WireId wire) const;
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void bindWire(WireId wire, NetInfo *net, PlaceStrength strength);
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void unbindWire(WireId wire);
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bool checkWireAvail(WireId wire) const;
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NetInfo *getBoundWireNet(WireId wire) const;
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WireId getConflictingWireWire(WireId wire) const { return wire; }
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NetInfo *getConflictingWireNet(WireId wire) const;
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DelayInfo getWireDelay(WireId wire) const { return DelayInfo(); }
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const std::vector<WireId> &getWires() const;
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const std::vector<BelPin> &getWireBelPins(WireId wire) const;
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PipId getPipByName(IdString name) const;
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IdString getPipName(PipId pip) const;
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IdString getPipType(PipId pip) const;
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const std::map<IdString, std::string> &getPipAttrs(PipId pip) const;
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uint32_t getPipChecksum(PipId pip) const;
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void bindPip(PipId pip, NetInfo *net, PlaceStrength strength);
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void unbindPip(PipId pip);
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bool checkPipAvail(PipId pip) const;
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NetInfo *getBoundPipNet(PipId pip) const;
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WireId getConflictingPipWire(PipId pip) const;
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NetInfo *getConflictingPipNet(PipId pip) const;
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const std::vector<PipId> &getPips() const;
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Loc getPipLocation(PipId pip) const;
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WireId getPipSrcWire(PipId pip) const;
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WireId getPipDstWire(PipId pip) const;
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DelayInfo getPipDelay(PipId pip) const;
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const std::vector<PipId> &getPipsDownhill(WireId wire) const;
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const std::vector<PipId> &getPipsUphill(WireId wire) const;
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GroupId getGroupByName(IdString name) const;
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IdString getGroupName(GroupId group) const;
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std::vector<GroupId> getGroups() const;
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const std::vector<BelId> &getGroupBels(GroupId group) const;
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const std::vector<WireId> &getGroupWires(GroupId group) const;
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const std::vector<PipId> &getGroupPips(GroupId group) const;
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const std::vector<GroupId> &getGroupGroups(GroupId group) const;
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delay_t estimateDelay(WireId src, WireId dst) const;
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delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
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delay_t getDelayEpsilon() const { return 0.001; }
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delay_t getRipupDelayPenalty() const { return 0.015; }
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float getDelayNS(delay_t v) const { return v; }
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DelayInfo getDelayFromNS(float ns) const
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{
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DelayInfo del;
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del.delay = ns;
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return del;
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}
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uint32_t getDelayChecksum(delay_t v) const { return 0; }
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bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const;
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ArcBounds getRouteBoundingBox(WireId src, WireId dst) const;
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bool pack();
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bool place();
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bool route();
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const std::vector<GraphicElement> &getDecalGraphics(DecalId decal) const;
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DecalXY getBelDecal(BelId bel) const;
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DecalXY getWireDecal(WireId wire) const;
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DecalXY getPipDecal(PipId pip) const;
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DecalXY getGroupDecal(GroupId group) const;
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bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
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// Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
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TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const;
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// Get the TimingClockingInfo of a port
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TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const;
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bool isValidBelForCell(CellInfo *cell, BelId bel) const;
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bool isBelLocationValid(BelId bel) const;
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static const std::string defaultPlacer;
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static const std::vector<std::string> availablePlacers;
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static const std::string defaultRouter;
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static const std::vector<std::string> availableRouters;
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// ---------------------------------------------------------------
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// Internal usage
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void assignArchInfo();
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bool cellsCompatible(const CellInfo **cells, int count) const;
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};
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NEXTPNR_NAMESPACE_END
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