305 lines
11 KiB
C++
305 lines
11 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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#include "viaduct_api.h"
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#include "viaduct_helpers.h"
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#define GEN_INIT_CONSTIDS
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#define VIADUCT_CONSTIDS "viaduct/example/constids.inc"
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#include "viaduct_constids.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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struct ExampleImpl : ViaductAPI
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{
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~ExampleImpl(){};
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void init(Context *ctx) override
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{
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init_uarch_constids(ctx);
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ViaductAPI::init(ctx);
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h.init(ctx);
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init_wires();
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init_bels();
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init_pips();
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}
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void pack() override
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{
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// Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
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const pool<CellTypePort> top_ports{
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CellTypePort(id_INBUF, id_PAD),
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CellTypePort(id_OUTBUF, id_PAD),
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};
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h.remove_nextpnr_iobs(top_ports);
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// Replace constants with LUTs
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const dict<IdString, Property> vcc_params = {{id_INIT, Property(0xFFFF, 16)}};
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const dict<IdString, Property> gnd_params = {{id_INIT, Property(0x0000, 16)}};
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h.replace_constants(CellTypePort(id_LUT4, id_F), CellTypePort(id_LUT4, id_F), vcc_params, gnd_params);
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// Constrain directly connected LUTs and FFs together to use dedicated resources
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int lutffs = h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
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log_info("Constrained %d LUTFF pairs.\n", lutffs);
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}
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void prePlace() override { assign_cell_info(); }
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bool isBelLocationValid(BelId bel, bool explain_invalid) const override
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{
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Loc l = ctx->getBelLocation(bel);
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if (is_io(l.x, l.y)) {
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return true;
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} else {
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return slice_valid(l.x, l.y, l.z / 2);
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}
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}
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private:
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ViaductHelpers h;
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// Configuration
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// Grid size including IOBs at edges
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const int X = 32, Y = 32;
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// SLICEs per tile
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const int N = 8;
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// LUT input count
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const int K = 4;
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// Number of local wires
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const int Wl = N * (K + 1) + 8;
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// 1/Fc for bel input wire pips; local wire pips and neighbour pips
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const int Si = 4, Sq = 4, Sl = 8;
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// For fast wire lookups
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struct TileWires
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{
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std::vector<WireId> clk, q, f, d, i;
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std::vector<WireId> l;
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std::vector<WireId> pad;
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};
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std::vector<std::vector<TileWires>> wires_by_tile;
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// Create wires to attach to bels and pips
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void init_wires()
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{
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log_info("Creating wires...\n");
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wires_by_tile.resize(Y);
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for (int y = 0; y < Y; y++) {
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auto &row_wires = wires_by_tile.at(y);
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row_wires.resize(X);
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for (int x = 0; x < X; x++) {
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auto &w = row_wires.at(x);
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for (int z = 0; z < N; z++) {
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// Clock input
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w.clk.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("CLK%d", z)), ctx->id("CLK"), x, y));
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// FF input
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w.d.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("D%d", z)), ctx->id("D"), x, y));
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// FF and LUT outputs
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w.q.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("Q%d", z)), ctx->id("Q"), x, y));
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w.f.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("F%d", z)), ctx->id("F"), x, y));
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// LUT inputs
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for (int i = 0; i < K; i++)
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w.i.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("L%dI%d", z, i)), ctx->id("I"), x, y));
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}
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// Local wires
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for (int l = 0; l < Wl; l++)
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w.l.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("LOCAL%d", l)), ctx->id("LOCAL"), x, y));
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// Pad wires for IO
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if (is_io(x, y) && x != y)
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for (int z = 0; z < 2; z++)
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w.pad.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("PAD%d", z)), id_PAD, x, y));
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}
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}
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}
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bool is_io(int x, int y) const
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{
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// IO are on the edges of the device
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return (x == 0) || (x == (X - 1)) || (y == 0) || (y == (Y - 1));
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}
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// Create IO bels in an IO tile
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void add_io_bels(int x, int y)
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{
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auto &w = wires_by_tile.at(y).at(x);
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for (int z = 0; z < 2; z++) {
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BelId b = ctx->addBel(h.xy_id(x, y, ctx->idf("IO%d", z)), id_IOB, Loc(x, y, z), false, false);
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ctx->addBelInout(b, id_PAD, w.pad.at(z));
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ctx->addBelInput(b, id_I, w.i.at(z * K + 0));
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ctx->addBelInput(b, id_EN, w.i.at(z * K + 1));
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ctx->addBelOutput(b, id_O, w.q.at(z));
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}
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}
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PipId add_pip(Loc loc, WireId src, WireId dst, delay_t delay = 0.05)
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{
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IdStringList name = IdStringList::concat(ctx->getWireName(dst), ctx->getWireName(src));
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return ctx->addPip(name, ctx->id("PIP"), src, dst, delay, loc);
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}
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// Create LUT and FF bels in a logic tile
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void add_slice_bels(int x, int y)
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{
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auto &w = wires_by_tile.at(y).at(x);
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for (int z = 0; z < N; z++) {
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// Create LUT bel
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BelId lut = ctx->addBel(h.xy_id(x, y, ctx->idf("SLICE%d_LUT", z)), id_LUT4, Loc(x, y, z * 2), false, false);
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for (int k = 0; k < K; k++)
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ctx->addBelInput(lut, ctx->idf("I[%d]", k), w.i.at(z * K + k));
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ctx->addBelOutput(lut, id_F, w.f.at(z));
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// FF data can come from LUT output or LUT I3
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add_pip(Loc(x, y, 0), w.f.at(z), w.d.at(z));
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add_pip(Loc(x, y, 0), w.i.at(z * K + (K - 1)), w.d.at(z));
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// Create DFF bel
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BelId dff =
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ctx->addBel(h.xy_id(x, y, ctx->idf("SLICE%d_FF", z)), id_DFF, Loc(x, y, z * 2 + 1), false, false);
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ctx->addBelInput(dff, id_CLK, w.clk.at(z));
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ctx->addBelInput(dff, id_D, w.d.at(z));
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ctx->addBelOutput(dff, id_Q, w.q.at(z));
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}
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}
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// Create bels according to tile type
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void init_bels()
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{
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log_info("Creating bels...\n");
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for (int y = 0; y < Y; y++) {
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for (int x = 0; x < X; x++) {
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if (is_io(x, y)) {
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if (x == y)
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continue; // don't put IO in corners
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add_io_bels(x, y);
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} else {
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add_slice_bels(x, y);
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}
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}
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}
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}
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// Create PIPs inside a tile; following an example synthetic routing pattern
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void add_tile_pips(int x, int y)
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{
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auto &w = wires_by_tile.at(y).at(x);
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Loc loc(x, y, 0);
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auto create_input_pips = [&](WireId dst, int offset, int skip) {
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for (int i = (offset % skip); i < Wl; i += skip)
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add_pip(loc, w.l.at(i), dst, 0.05);
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};
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for (int z = 0; z < N; z++) {
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create_input_pips(w.clk.at(z), 0, Si);
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for (int k = 0; k < K; k++)
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create_input_pips(w.i.at(z * K + k), k, Si);
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}
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auto create_output_pips = [&](WireId dst, int offset, int skip) {
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for (int z = (offset % skip); z < N; z += skip) {
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add_pip(loc, w.f.at(z), dst, 0.05);
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add_pip(loc, w.q.at(z), dst, 0.05);
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}
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};
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auto create_neighbour_pips = [&](WireId dst, int nx, int ny, int offset, int skip) {
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if (nx < 0 || nx >= X)
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return;
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if (ny < 0 || ny >= Y)
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return;
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auto &nw = wires_by_tile.at(ny).at(nx);
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for (int i = (offset % skip); i < Wl; i += skip)
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add_pip(loc, dst, nw.l.at(i), 0.1);
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};
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for (int i = 0; i < Wl; i++) {
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WireId dst = w.l.at(i);
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create_output_pips(dst, i % Sq, Sq);
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create_neighbour_pips(dst, x - 1, y - 1, (i + 1) % Sl, Sl);
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create_neighbour_pips(dst, x - 1, y, (i + 2) % Sl, Sl);
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create_neighbour_pips(dst, x - 1, y + 1, (i + 3) % Sl, Sl);
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create_neighbour_pips(dst, x, y - 1, (i + 4) % Sl, Sl);
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create_neighbour_pips(dst, x, y + 1, (i + 5) % Sl, Sl);
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create_neighbour_pips(dst, x + 1, y - 1, (i + 6) % Sl, Sl);
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create_neighbour_pips(dst, x + 1, y, (i + 7) % Sl, Sl);
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create_neighbour_pips(dst, x + 1, y + 1, (i + 8) % Sl, Sl);
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}
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}
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void init_pips()
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{
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log_info("Creating pips...\n");
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for (int y = 0; y < Y; y++)
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for (int x = 0; x < X; x++)
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add_tile_pips(x, y);
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}
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// Validity checking
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struct ExampleCellInfo
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{
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const NetInfo *lut_f = nullptr, *ff_d = nullptr;
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bool lut_i3_used = false;
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};
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std::vector<ExampleCellInfo> fast_cell_info;
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void assign_cell_info()
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{
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fast_cell_info.resize(ctx->cells.size());
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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auto &fc = fast_cell_info.at(ci->flat_index);
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if (ci->type == id_LUT4) {
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fc.lut_f = ci->getPort(id_F);
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fc.lut_i3_used = (ci->getPort(ctx->idf("I[%d]", K - 1)) != nullptr);
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} else if (ci->type == id_DFF) {
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fc.ff_d = ci->getPort(id_D);
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}
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}
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}
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bool slice_valid(int x, int y, int z) const
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{
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const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
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const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
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if (!lut || !ff)
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return true; // always valid if only LUT or FF used
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const auto &lut_data = fast_cell_info.at(lut->flat_index);
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const auto &ff_data = fast_cell_info.at(ff->flat_index);
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// In our example arch; the FF D can either be driven from LUT F or LUT I3
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// so either; FF D must equal LUT F or LUT I3 must be unused
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if (ff_data.ff_d == lut_data.lut_f)
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return true;
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if (lut_data.lut_i3_used)
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return false;
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return true;
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}
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// Bel bucket functions
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IdString getBelBucketForCellType(IdString cell_type) const override
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{
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if (cell_type.in(id_INBUF, id_OUTBUF))
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return id_IOB;
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return cell_type;
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}
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bool isValidBelForCellType(IdString cell_type, BelId bel) const override
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{
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IdString bel_type = ctx->getBelType(bel);
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if (bel_type == id_IOB)
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return cell_type.in(id_INBUF, id_OUTBUF);
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else
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return (bel_type == cell_type);
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}
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};
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struct ExampleArch : ViaductArch
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{
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ExampleArch() : ViaductArch("example"){};
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std::unique_ptr<ViaductAPI> create(const dict<std::string, std::string> &args)
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{
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return std::make_unique<ExampleImpl>();
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}
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} exampleArch;
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} // namespace
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NEXTPNR_NAMESPACE_END
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