nextpnr/himbaechel/uarch/gowin
YRabbit 78ee20b5da gowin: Himbaechel. Extend clock router
Now the clock router can place a buffer into the specified network,
which divides the network into two parts: from the source to the buffer,
routing occurs through any available PIPs, and after the buffer to the
sink, only through a dedicated global clock network.

This is made specifically for the Tangnano20k where the external
oscillator is soldered to a regular non-clock pin. But it can be used
for other purposes, you just need to remember that the recipient must be
a CLK input or output pin.

The port/network to set the buffer to is specified in the .CST file:

CLOCK_LOC "name" BUFG;

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-09-08 09:15:35 +02:00
..
CMakeLists.txt himbaechel/gowin: recognize -DAPYCULA_INSTALL_PREFIX=.../virtualenv. 2023-09-07 10:47:54 +02:00
constids.inc gowin: Himbaechel. Extend clock router 2023-09-08 09:15:35 +02:00
cst.cc gowin: Himbaechel. Extend clock router 2023-09-08 09:15:35 +02:00
cst.h gowin: Himbaechel. Add constraint file processing. 2023-08-31 08:28:09 +02:00
globals.cc gowin: Himbaechel. Extend clock router 2023-09-08 09:15:35 +02:00
globals.h gowin: Himbaechel. Add a clock router. 2023-08-31 08:28:09 +02:00
gowin_arch_gen.py gowin: Himbaechel. Extend clock router 2023-09-08 09:15:35 +02:00
gowin_utils.cc gowin: Himbaechel. Add OSER16 and IDES16 2023-08-31 08:28:09 +02:00
gowin_utils.h gowin: Himbaechel. Add OSER16 and IDES16 2023-08-31 08:28:09 +02:00
gowin.cc gowin: Himbaechel. Handling of disabled units 2023-08-31 08:28:09 +02:00
gowin.h gowin: Himbaechel. Extend clock router 2023-09-08 09:15:35 +02:00
pack.cc gowin: Himbaechel. Extend clock router 2023-09-08 09:15:35 +02:00
pack.h gowin: Himbaechel. Add ALU. 2023-08-31 08:28:09 +02:00