3611f54902
* load wires
* add slice bels
* add IOB
* add aliases
* local aliases
* broken packing stuff
* working packer
* add constraints
* pnr runs1111
* add timing info
* constraints
* more constraint stuff
* add copyright
* remove generic reference
* remove parameters
* remove generic python api
* add newline to end of file
* some small refactoring
* warn on invalid constraints
* don't error on missing cell
* comment out debugging print
* typo
* avoid copy
* faster empty idstring
* remove intermediate variable
* no more deadnames
* fix cst warnings
* increase ripup and epsilon a bit
* take single device parameter
* add info to readme
* gui stubs
* Revert 4d03b681a8
* assign ff_used in assignArchInfo
* decrease beta for better routability
* try to fix CI
95 lines
2.9 KiB
C++
95 lines
2.9 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2019 David Shah <david@symbioticeda.com>
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* Copyright (C) 2020 Pepijn de Vos <pepijn@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "nextpnr.h"
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#ifndef GENERIC_CELLS_H
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#define GENERIC_CELLS_H
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NEXTPNR_NAMESPACE_BEGIN
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// Create a generic arch cell and return it
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// Name will be automatically assigned if not specified
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std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::string name = "");
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// Return true if a cell is a LUT
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inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell)
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{
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switch (cell->type.index) {
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case ID_LUT1:
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case ID_LUT2:
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case ID_LUT3:
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case ID_LUT4:
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return true;
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default:
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return false;
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}
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}
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// Return true if a cell is a flipflop
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inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell)
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{
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switch (cell->type.index) {
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case ID_DFF:
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case ID_DFFE:
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case ID_DFFS:
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case ID_DFFSE:
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case ID_DFFR:
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case ID_DFFRE:
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case ID_DFFP:
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case ID_DFFPE:
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case ID_DFFC:
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case ID_DFFCE:
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case ID_DFFN:
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case ID_DFFNE:
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case ID_DFFNS:
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case ID_DFFNSE:
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case ID_DFFNR:
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case ID_DFFNRE:
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case ID_DFFNP:
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case ID_DFFNPE:
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case ID_DFFNC:
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case ID_DFFNCE:
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return true;
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default:
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return false;
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}
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}
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inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SLICE; }
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// Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports
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// as needed. Set no_dff if a DFF is not being used, so that the output
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// can be reconnected
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void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff = true);
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// Convert a DFF primitive to (part of) an GENERIC_SLICE, setting parameters
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// and reconnecting signals as necessary. If pass_thru_lut is True, the LUT will
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// be configured as pass through and D connected to I0, otherwise D will be
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// ignored
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void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut = false);
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// Convert a Gowin IO buffer to a IOB bel
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void gwio_to_iob(Context *ctx, CellInfo *nxio, CellInfo *sbio, std::unordered_set<IdString> &todelete_cells);
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NEXTPNR_NAMESPACE_END
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#endif
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