Pepijn de Vos 7c362f292c dedicated output for LUT in GENERIC_SLICE		2019-11-08 15:54:27 +01:00
..
cells_map.v	generic: Add synth_generic.tcl	2019-04-02 15:30:01 +01:00
prims.v	dedicated output for LUT in GENERIC_SLICE	2019-11-08 15:54:27 +01:00
synth_generic.tcl	generic: Simple working example	2019-04-02 15:30:01 +01:00